A multilayer framework supporting autonomous run-time partial reconfiguration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 16, Issue 5, 2008, Pages 504-516

  Tan, Heng ^b   DeMara, Ronald F ^a,b  

^a IEEE

^b University of Central Florida   (United States)

Author keywords

Bitstream manipulation; Field programmable gate array (FPGA) area management; FPGA run time environments; Frame based partial reconfiguration; Module based partial reconfiguration

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMMING INTERFACES (API); CONTROL SYSTEMS; RANDOM ACCESS STORAGE;

BITSTREAM MANIPULATION; FPGA RUN-TIME ENVIRONMENTS; FRAME-BASED PARTIAL RECONFIGURATION; MODULE-BASED PARTIAL RECONFIGURATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 42649145856     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.917551     Document Type: Article

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