PaDReH - A framework for the design and implementation of dynamically and partially reconfigurable systems

Proceedings - 17th Symposium on Integrated Cicuits and Systems Design, SBCCI2004

Volumn , Issue , 2004, Pages 10-15

  Carvalho, Ewerson ^a   Calazans, Ney ^a   Brião, Eduardo ^a   Moraes, Fernando ^a  

^a PONTIFICAL CATHOLIC UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Dynamically and partially reconfigurable systems; Partial bitstream generation; Reconfiguration control; Run time reconfiguration

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER SOFTWARE; PROJECT MANAGEMENT; VLSI CIRCUITS;

DYNAMICALLY AND PARTIALLY RECONFIGURABLE SYSTEMS; PARTIAL BITSTREAM GENERATION; RECONFIGURATION CONTROL; RUN-TIME CONFIGURATION;

SYSTEMS ANALYSIS;

EID: 14244261385     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. Zhang, X., and Ng, K. W. A review of high-level synthesis for dynamically reconfigurable FPGAs. Microprocessors and Microsystems, v. 24, p. 199-211, 2000.
2. Bergamaschi R., and Lee, W. Designing system-on-chip using cores. In DAC'00, pp. 420-425. USA. 2000.
3. DeHon, A. Comparing Computing Machines. In Proc. SPIE Configurable Computing: Technology and Applications, v. 3526, pp. 124-133, 1998.
4. Caspi, E., DeHon, A., and Wawrzynek, J. A streaming multithreaded model, In: Third Workshop on Media and Stream Processors, 2001.
5. Lehn, D., Hudson, R., and Athanas, P. Framework for architecture- independent run-time reconfigurable applications, In: SPIE Proceedings, November, 2000.
6. Edwards, M., and Green, P. Run-time support for dynamically reconfigurable computing systems. Journal of Systems Architecture, v. 49, pp. 267-281, 2003
7. Bapty, T., Neema, S., Scott, J., Sztipanovits, J., and Asaad, S. Model-integrated tools for the design of dynamically reconfigurable systems, Technical Report #ISIS-99-01, ISIS, Vanderbilt University, 2000.
8. Natarajan, S., Levine, B., Tan, C., Newport, D., and Bouldin, D. Automatic Mapping of Khoros-based Applications to Adaptive Computing Systems. In: MAPLD'99, pp. 101-107, 1999.
9. Eisenring, M., and Platzner, M. A framework for run-time reconfigurable systems, Journal of Supercomputing v. 21, pp. 145-159, 2002.
10. Ouaiss, I., Govindarajan, S., Srinivasan, V., Kaul, M., and Vemuri, R. An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures. In: RAW'98, 1998.
11. James-Roxby, P.; Guccione, S. Automated extraction of run-time parameterisable cores from programmable device configurations. In: FCCM'00. pp. 153-161, 2000.
12. Xilinx, Inc. The JBits 3.0 SDK for Virtex-II. 2003. Available at http://www.xilinx.com/labs/downloads/jbits/index.htm
13. Horta, E., Lockwood, J., and Kofuji, S. Using PARBIT to implement Partial Run-time Reconfigurable Systems. In: FPL '02, pp 182-191, 2002.
14. Raghavan, A., and Sutton, P. JPG - a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs. In: IPDPS'02, pp. 155-160, 2002.
15. Xilinx, Inc. Two Flows for Partial Reconfiguration: Module Based or Difference Based. Xilinx Application Note XAPP290, V1.1. 2003.
16. Palma, J., Mello, A., Möller, L., Moraes, F. and Calazans, N. Core Communication Interface for FPGAs. In SBCCI'02, pp. 183-188, 2002.
17. Brião, E. Partial and Dynamic Reconfiguration for Intellectual Property Cores, MSc Dissertation, PUCRS-PPGCC-FACIN, Porto Alegre, Brazil, 2004. (In Portuguese)
18. Carvalho, E. RSCM: Configuration Control for Reconfigurable Hardware Systems, MSc Dissertation, PUCRS-PPGCC-FACIN, Porto Alegre, Brazil, 2004. (In Portuguese)
19. Moraes, F., and Calazans, N. R8 Processor Architecture and Organization Specification and Design Guidelines. 2003. Available at http://www.inf.pucrs.br/ ~gaph/Projects/R8/public/R8_arq_spec_eng.pdf