Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2011, Pages 1208-1211

  Vidal, Jorgiano ^a   De Lamotte, Florent ^a   Gogniat, Guy ^a   Diguet, Jean Philippe ^a   Guillet, Sebastien ^a  

^a UNIVERSITÉ EUROPÉENNE DE BRETAGNE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OPTIMIZATION; AREA REDUCTION; AUTOMATICALLY GENERATED; CO-PROCESSORS; DESIGN METHODOLOGY; DESIGN PATTERNS; DESIGN TIME; DYNAMIC AND PARTIAL RECONFIGURATION; DYNAMIC APPLICATIONS; DYNAMIC BEHAVIORS; EMBEDDED PROCESSORS; FPGAS IMPLEMENTATION; HARDWARE AND SOFTWARE; MODELING APPROACH; MULTI PROCESSOR SYSTEMS; PARTIAL RECONFIGURATION; PERFORMANCE PENALTIES; RECONFIGURABLE SYSTEMS; SET OF RULES; SPEED-UPS; SYSTEM FLEXIBILITY; TARGET DYNAMICS; UML MODEL;

DYNAMIC MODELS; RECONFIGURABLE HARDWARE; UNIFIED MODELING LANGUAGE;

STRUCTURAL DESIGN;

EID: 79957545685     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. OMG, "Unified Modeling Language Specification," Object Management Group, Technical Report/2002-05-08, Specification formal/07-02-03, february 2002. [Online]. Available: http://www.omg.org
2. A. Koudri, D. Vojtsiek, P. Soulard, C. Moy, J. Champeau, J. Vidal, and J.-c. Le lann, "Using marte in the mopcom soc/sopc methodology," in workshop MARTE, 03 2008.
3. J. Dekeyser, P. Boulet, P. Marquet, and S. Meftali, "Model driven engineering for soc co-design," IEEE-NEWCAS Conference, 2005. The 3rd International, pp. 21-25, 2005.
4. C.-H. Tseng and P.-A. Hsiung, "UML-Based Design Flow and Partitioning Methodology for Dynamically Reconfigurable Computing Systems." in EUC, 2005, pp. 479-488.
5. Imran Rafiq Quadri, Samy Meftali, and Jean-Luc Dekeyser, "High level modeling of dynamic reconfigurable FPGAs," International Journal of Reconfigurable Computing, vol. 2009, p. 15, 2009.
6. F. WEST Team LIFL, Lille, "Graphical array specification for parallel and distributed computing (gaspard-2)," 2005. [Online]. Available: http://www2.lifl.fr/west/gaspard/
7. P. Bomel, J. Crenne, L. Ye, J.-P. Diguet, and G. Gogniat, "Ultrafast downloading of partial bitstreams through ethernet," in ARCS, ser. Lecture Notes in Computer Science, M. Berekovic, C. Müller-Schloer, C. Hochberger, and S. Wong, Eds., vol. 5455. Springer, 2009, pp. 72-83.
8. J. Vidal, F. de Lamotte, G. Gogniat, P. Soulard, and J.-P. Diguet, "A co-design approach for embedded system modeling and code generation with uml and marte," in DATE '09: Proceedings of the conference on Design, automation and test in Europe, 2009.
9. J. Vidal, F. de Lamotte, G. Gogniat, J.-P. Diguet, and P. Soulard, "Ip reuse in an mda mpsopc co-design approach," in ICM'09: Proceedings of the International Conference on Microeletronics, 2009.
10. -, "Uml design for dynamically reconfigurable multiprocessor embedded systems," in DATE. IEEE, 2010, pp. 1195-1200.
11. E. Gamma, R. Helm, R. E. Johnson, and J. Vlissides, Design Patterns: Elements of Reusable Object-Oriented Software. Reading, MA: Addison-Wesley, 1995.
12. X. INC, "Xup development board." [Online]. Available: http://www.xilinx.com/products/devkits/XUPV2P.htm