GePaRD - A High-Level generation flow for Partially Reconfigurable designs

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008

Volumn , Issue , 2008, Pages 298-303

  Boden, Maik ^a   Fiebig, Thomas ^a   Reiband, Markus ^a   Reichel, Peter ^a   Rülke, Steffen ^a  

^a FRAUNHOFER INSTITUTE FOR INTEGRATED CIRCUITS   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; ANNEALING; MODULAR CONSTRUCTION; TECHNOLOGY;

CLIQUE PARTITIONING; DESIGN STEPS; HIGH-LEVEL SYNTHESIS; MODULARIZATION; RE-CONFIGURABLE; RECONFIGURABLE DESIGNS; RECONFIGURATION OVERHEAD; REUSABLE MODULES; RUN-TIME; SELF-ADAPTIVE SYSTEMS; VLSI TECHNOLOGIES;

SIMULATED ANNEALING;

EID: 51849098993     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2008.21     Document Type: Conference Paper

References (11)

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