-
1
-
-
84948746212
-
Electrostatic discharge and failure analysis: Models, methods, and mechanisms
-
Invited Talk Singapore July
-
S. Voldman, "Electrostatic Discharge and Failure Analysis: Models, Methods, and Mechanisms," Invited Talk, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, Singapore, pp.57-65, July 2002.
-
(2002)
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits
, pp. 57-65
-
-
Voldman, S.1
-
3
-
-
0038523683
-
Lightning rods for nanostructures
-
October edition
-
S. Voldman, "Lightning Rods for Nanostructures," Scientific American, October edition, 2002.
-
(2002)
Scientific American
-
-
Voldman, S.1
-
4
-
-
0037691091
-
Analysis of latchup prevention in CMOS IC's using epitaxial buried layer process
-
D. B. Estreich, "Analysis of Latchup Prevention in CMOS IC's Using Epitaxial Buried Layer Process," IEDM Technical Digest, 1978.
-
(1978)
IEDM Technical Digest
-
-
Estreich, D.B.1
-
6
-
-
0020909950
-
Epitaxial layer enhancement of N-well guard rings for CMOS circuits
-
Dec.
-
R. Troutman, "Epitaxial Layer Enhancement of N-Well Guard Rings for CMOS Circuits," IEEE Trans. On Elec. Dev. Letters, Vol ED-4, pp.438-440, Dec. 1983.
-
(1983)
IEEE Trans. on Elec. Dev. Letters
, vol.ED-4
, pp. 438-440
-
-
Troutman, R.1
-
7
-
-
0038185073
-
The physics and modelling of latchup and CMOS integrated circuits
-
November
-
D. B. Estreich, "The Physics and Modelling of Latchup and CMOS Integrated Circuits," Integrated Circuits Laboratory, November 1980.
-
(1980)
Integrated Circuits Laboratory
-
-
Estreich, D.B.1
-
8
-
-
0020704130
-
A transient analysis of latchup in bulk CMOS
-
ED-30 Feb.
-
R. R. Troutman, and H.P. Zappe, "A Transient Analysis of Latchup in Bulk CMOS, "IEEE Trans. Elec. Dev., ED-30, pp. 170-179, Feb. 1983.
-
(1983)
IEEE Trans. Elec. Dev.
, pp. 170-179
-
-
Troutman, R.R.1
Zappe, H.P.2
-
9
-
-
0020891350
-
Latchup immunity against noise pulses in a CMOS double well structure
-
Dec.
-
G. Goto, H. Takahashi, and T. Nakamura, "Latchup Immunity Against Noise Pulses in a CMOS Double Well Structure," IEDM Technical Digest, pp. 168-171, Dec. 1983.
-
(1983)
IEDM Technical Digest
, pp. 168-171
-
-
Goto, G.1
Takahashi, H.2
Nakamura, T.3
-
10
-
-
0021201527
-
Latchup model for parasitic path in bulk CMOS
-
Jan.
-
R. C. Fang and J. L. Moll, "Latchup Model for Parasitic Path in Bulk CMOS," IEEE Trans. Elec. Devices, ED-31, pp. 113-120, Jan. 1984.
-
(1984)
IEEE Trans. Elec. Devices
, vol.ED-31
, pp. 113-120
-
-
Fang, R.C.1
Moll, J.L.2
-
11
-
-
0021204461
-
A better understanding of CMOS latchup
-
Jan.
-
G. Hu, "A Better Understanding of CMOS Latchup," IEEE Trans. Elec. Dev. ED-31, pp. 62-67, Jan. 1984.
-
(1984)
IEEE Trans. Elec. Dev.
, vol.ED-31
, pp. 62-67
-
-
Hu, G.1
-
12
-
-
0022757469
-
Transmission line modeling of substrate resistance and CMOS latchup
-
July
-
R. R. Troutman and M.J. Hargrove, "Transmission Line Modeling of Substrate Resistance and CMOS Latchup," IEEE Trans. Elec. Dev., July 1986.
-
(1986)
IEEE Trans. Elec. Dev.
-
-
Troutman, R.R.1
Hargrove, M.J.2
-
13
-
-
0021390632
-
Layout and bias considerations for preventing transient triggered latchup in CMOS
-
March
-
R.R. Troutman, and H.P. Zappe, "Layout and Bias Considerations for Preventing Transient Triggered Latchup in CMOS," IEEE Trans. Elec. Dev. ED-31. pp. 315-321, March 1984.
-
(1984)
IEEE Trans. Elec. Dev.
, vol.ED-31
, pp. 315-321
-
-
Troutman, R.R.1
Zappe, H.P.2
-
14
-
-
28744434587
-
Retrograde well and epitaxial thickness optimization for shallow-and deep-trench collar merged isolation and node trench SPT cell and CMOS logic technology
-
S. Voldman, M. Marceau, A. Baker, E. Adler, S. Geissler, J. Slinkman, J. Johnson, and M. Paggi, "Retrograde well and epitaxial thickness optimization for shallow-and deep-trench collar merged isolation and node Trench SPT cell and CMOS Logic Technology," IEDM Technical Digest, pp.811-815, 1992.
-
(1992)
IEDM Technical Digest
, pp. 811-815
-
-
Voldman, S.1
Marceau, M.2
Baker, A.3
Adler, E.4
Geissler, S.5
Slinkman, J.6
Johnson, J.7
Paggi, M.8
-
16
-
-
0029405952
-
MeV implants boost device design
-
Nov.
-
S. Voldman, "MeV Implants Boost Device Design," IEEE Circuits and Devices, Vol. 11, No. 6, pp.8-16, Nov. 1995.
-
(1995)
IEEE Circuits and Devices
, vol.11
, Issue.6
, pp. 8-16
-
-
Voldman, S.1
-
17
-
-
0031707249
-
Latchup in CMOS
-
Invited Talk April
-
M. Hargrove, S. Voldman, J. Brown, K. Duncan, and W. Craig, "Latchup in CMOS," Invited Talk, International Reliability Physics Symposium, April 1998, pp.269-278.
-
(1998)
International Reliability Physics Symposium
, pp. 269-278
-
-
Hargrove, M.1
Voldman, S.2
Brown, J.3
Duncan, K.4
Craig, W.5
-
19
-
-
84937349208
-
Determination of threshold failure levels of semiconductor diodes and transistors due to pulse voltage
-
NS-15 Dec.
-
D.C. Wunsch and R.R. Bell, "Determination of Threshold Failure Levels of Semiconductor diodes and transistors due to Pulse Voltage," IEEE Transactions of Nuclear Science, NS-15, pp. 244-236, Dec. 1988.
-
(1988)
IEEE Transactions of Nuclear Science
, pp. 244-236
-
-
Wunsch, D.C.1
Bell, R.R.2
-
20
-
-
35148815587
-
Pulse power failure modes in semiconductors
-
Dec.
-
D. M. Tasca, "Pulse Power Failure Modes in Semiconductors," IEEE Transactions on Nuclear Science, NS-17, pp.364-372, Dec. 1970.
-
(1970)
IEEE Transactions on Nuclear Science
, vol.NS-17
, pp. 364-372
-
-
Tasca, D.M.1
-
21
-
-
84939713074
-
Semiconductor device degradation by high amplitude current pulses
-
December
-
W.D. Brown, "Semiconductor Device Degradation by High Amplitude Current Pulses," IEEE Transactions of Nuclear Science," NS-19, pp.68-75, December 1972.
-
(1972)
IEEE Transactions of Nuclear Science
, vol.NS-19
, pp. 68-75
-
-
Brown, W.D.1
-
22
-
-
0005973237
-
Square pulse and RF pulse overstressing of UHF transistors
-
J. Whalen and H. Domingos, "Square Pulse and RF Pulse Overstressing of UHF Transistors," EOS/ESD Symposium, pp.140-146, 1979.
-
(1979)
EOS/ESD Symposium
, pp. 140-146
-
-
Whalen, J.1
Domingos, H.2
-
23
-
-
0022212124
-
Transmission line pulse technique for circuit modeling and ESD phenomena
-
T. Maloney and N. Khurana, "Transmission Line Pulse Technique for Circuit Modeling and ESD Phenomena," EOS/ESD Symposium Proceedings, pp.49-54, 1985.
-
(1985)
EOS/ESD Symposium Proceedings
, pp. 49-54
-
-
Maloney, T.1
Khurana, N.2
-
24
-
-
0022219373
-
ESD on CHMOS devices equivalent circuits, physical models, and failure mechanisms
-
Khurana, T. Maloney, W. Yeh, "ESD on CHMOS Devices Equivalent Circuits, Physical Models, and Failure Mechanisms," International Reliability Physics Symposium pp.212-223, 1985.
-
(1985)
International Reliability Physics Symposium
, pp. 212-223
-
-
Khurana1
Maloney, T.2
Yeh, W.3
-
25
-
-
0029227261
-
Modified transmission line pulse system and transistor test structures for the study of ESD
-
Nara, Japan
-
R. Ashton, "Modified Transmission Line Pulse System and Transistor Test Structures for the Study of ESD," in the Proceedings of the IEEE 1995 International Conference on Microelectronic Test Structures," Nara, Japan, Vol. 8, pp. 127-132, 1995.
-
(1995)
The Proceedings of the IEEE 1995 International Conference on Microelectronic Test Structures
, vol.8
, pp. 127-132
-
-
Ashton, R.1
-
26
-
-
0034538752
-
TLP calibration, correlation, standards, and new techniques
-
J. Barth, J. Richner, K. Verhaege, and L. G. Henry, "TLP Calibration, Correlation, Standards, and New Techniques," EOS/ESD Symposium Proceedings, pp.85-97, 2000.
-
(2000)
EOS/ESD Symposium Proceedings
, pp. 85-97
-
-
Barth, J.1
Richner, J.2
Verhaege, K.3
Henry, L.G.4
-
27
-
-
0034543580
-
TLP measurements for verification of ESD protection device response
-
H. Hyatt, J. Harris, A. Alanzo, P. Bellew, "TLP Measurements for Verification of ESD Protection Device Response," EOS/ESD Symposium Proceedings, pp.111-121, 2000.
-
(2000)
EOS/ESD Symposium Proceedings
, pp. 111-121
-
-
Hyatt, H.1
Harris, J.2
Alanzo, A.3
Bellew, P.4
-
28
-
-
0038523680
-
The application of TLP for the ESD analysis of integrated circuits
-
T. Smedes, R. Velghe, R. Ruth, A. Huitsing, "The Application of TLP for the ESD Analysis of Integrated Circuits," EOS/ESD Symposium Proceedings, 2001.
-
(2001)
EOS/ESD Symposium Proceedings
-
-
Smedes, T.1
Velghe, R.2
Ruth, R.3
Huitsing, A.4
-
29
-
-
84948986274
-
Contributions to standardization of transmission line pulse testing methodology
-
B. Keppens, V. De Heyn, N. Mahadeva, G. Groeseneken, "Contributions to Standardization of Transmission Line Pulse Testing Methodology," EOS/ESD Symposium Proceedings, 2001.
-
(2001)
EOS/ESD Symposium Proceedings
-
-
Keppens, B.1
De Heyn, V.2
Mahadeva, N.3
Groeseneken, G.4
-
30
-
-
0034538867
-
A method for determining a transmission line pulse shape that produces equivalent results to human body model testing methods
-
J. Lee, M. Hoque, J. Liou, G. Croft, W. Young, and J. Bemier, "A Method for Determining a Transmission Line Pulse Shape that Produces Equivalent Results to Human Body Model Testing Methods," EOS/ESD Symposium Proceedings, pp.97-105,2000.
-
(2000)
EOS/ESD Symposium Proceedings
, pp. 97-105
-
-
Lee, J.1
Hoque, M.2
Liou, J.3
Croft, G.4
Young, W.5
Bemier, J.6
-
31
-
-
84869020968
-
Correlation considerations: Real HBM to TLP and HBM testers
-
J. Barth, and J. Richter, "Correlation Considerations: Real HBM to TLP and HBM Testers," EOS/ESD Symposium Proceedings, 2001.
-
(2001)
EOS/ESD Symposium Proceedings
-
-
Barth, J.1
Richter, J.2
-
32
-
-
0030398616
-
Very fast transmission line pulse of integrated structures and the charged device model
-
H. Geiser et al., "Very fast transmission line pulse of integrated structures and the charged device model," EOS/ESD Symposium Proceedings, pp.85-94, 1996.
-
(1996)
EOS/ESD Symposium Proceedings
, pp. 85-94
-
-
Geiser, H.1
-
34
-
-
84945206072
-
Standardization of the transmission line pulse (TLP) methodology for electrostatic discharge (ESD)
-
Steven H. Voldman, Robert Ashton, Jon Barth, David Bennett, Joseph Bernier, Michael Chaine, Jeffrey Daughton, Evan Grund, Marti Farris, Horst Gieser, Leo G. Henry, Mike Hopkins, Hugh Hyatt, Natarajan Mahadeva Iyer, Patrick Juliano, Timothy J. Maloney, Larry Ting, and Eugene Worley, "Standardization of the Transmission Line Pulse (TLP) Methodology for Electrostatic Discharge (ESD)," EOS/ESD Symposium, 2003.
-
(2003)
EOS/ESD Symposium
-
-
Voldman, S.H.1
Ashton, R.2
Barth, J.3
Bennett, D.4
Bernier, J.5
Chaine, M.6
Daughton, J.7
Grund, E.8
Farris, M.9
Gieser, H.10
Henry, L.G.11
Hopkins, M.12
Hyatt, H.13
Iyer, N.M.14
Juliano, P.15
Maloney, T.J.16
Ting, L.17
Worley, E.18
-
35
-
-
0038257258
-
High current transmission line pulse characterization of aluminum and copper interconnects for advanced CMOS semiconductor technologies
-
S. Voldman et al., "High Current Transmission Line Pulse Characterization of Aluminum and Copper Interconnects for Advanced CMOS Semiconductor Technologies;," IRPS Symposium, pp.293-302, 1998.
-
(1998)
IRPS Symposium
, pp. 293-302
-
-
Voldman, S.1
-
36
-
-
0029700866
-
Characterization of VLSI circuit interconnect heating and failure under ESD conditions
-
K. Banerjee, "Characterization of VLSI Circuit Interconnect Heating and Failure under ESD Conditions," IRPS Proceedings, pp.237-245, 1996.
-
(1996)
IRPS Proceedings
, pp. 237-245
-
-
Banerjee, K.1
-
37
-
-
0031336109
-
ESD robustness and scaling implications of aluminum and copper interconnects in advanced semiconductor technology
-
S. Voldman, "ESD Robustness and Scaling Implications of Aluminum and Copper Interconnects in Advanced Semiconductor Technology," EOS/ESD Symposium, pp. 317-327, 1997.
-
(1997)
EOS/ESD Symposium
, pp. 317-327
-
-
Voldman, S.1
-
38
-
-
0032664172
-
High current characterization of dual damascene copper/SiO2 and low-K interievel dielectrics for advanced CMOS semiconductor technologies
-
S. Voldman et al., "High Current Characterization of Dual Damascene Copper/SiO2 and Low-K Interievel Dielectrics for Advanced CMOS Semiconductor Technologies," IRPS Symposium, pp.144-153, 1999.
-
(1999)
IRPS Symposium
, pp. 144-153
-
-
Voldman, S.1
-
39
-
-
0034542546
-
Silicon-on-insulator dynamic threshold ESD networks and active clamp circuitry
-
S. Voldman, J. Howard, M. Sherony, F. Assaderaghi, D. Hui, D. Young, D. Dreps, G. Shahidi, "Silicon-On-Insulator Dynamic Threshold ESD Networks and Active Clamp Circuitry," EOS/ESD Symposium, pp.29-40, 2000.
-
(2000)
EOS/ESD Symposium
, pp. 29-40
-
-
Voldman, S.1
Howard, J.2
Sherony, M.3
Assaderaghi, F.4
Hui, D.5
Young, D.6
Dreps, D.7
Shahidi, G.8
-
40
-
-
0033732439
-
Electrostatic discharge and high current pulse characterization of epitaxial base silicon germanium heterojunction bipolar transistors
-
March
-
S. Voldman et al., "Electrostatic Discharge and High Current Pulse Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors," IRPS Proceedings, March 2000.
-
(2000)
IRPS Proceedings
-
-
Voldman, S.1
-
41
-
-
0034544872
-
Electrostatic discharge characterization of epitaxial base silicon germanium heterojunction bipolar transistors
-
Sept.
-
S. Voldman, N. Schmidt, R. Johnson., L. Lanzerotti, A. Joseph, C. Brennan, J. Dunn, D. Harame, P. Juliano, E. Rosenbaum, and B. Meyerson, "Electrostatic Discharge Characterization of Epitaxial Base Silicon Germanium Heterojunction Bipolar Transistors," EOS/ESD Symposium, pp. 239-251, Sept. 2000.
-
(2000)
EOS/ESD Symposium
, pp. 239-251
-
-
Voldman, S.1
Schmidt, N.2
Johnson, R.3
Lanzerotti, L.4
Joseph, A.5
Brennan, C.6
Dunn, J.7
Harame, D.8
Juliano, P.9
Rosenbaum, E.10
Meyerson, B.11
-
42
-
-
0036088526
-
High current transmission line pulse (TLP) and ESD characterization of a silicon germanium heterojunction bipolar transistor with carbon incorporation
-
B. Ronan, S. Voldman, L. Lanzerotti, J. Rascoe, D. Sheridan, and K. Rajendran, "High Current Transmission Line Pulse (TLP) and ESD Characterization of a Silicon Germanium Heterojunction Bipolar Transistor with Carbon Incorporation," IRPS Proceedings, 2002.
-
(2002)
IRPS Proceedings
-
-
Ronan, B.1
Voldman, S.2
Lanzerotti, L.3
Rascoe, J.4
Sheridan, D.5
Rajendran, K.6
-
44
-
-
0035456920
-
Unique and practical 1C timing analysis tool utilizing intrinsic photon emission
-
N. Goldblatt, M. Leibowitz, and W. Lo, "Unique and practical 1C timing analysis tool utilizing intrinsic photon emission," in Microelectronic Reliability, Vol. 41, No.9-10, 2001, pp. 1507.
-
(2001)
Microelectronic Reliability
, vol.41
, Issue.9-10
, pp. 1507
-
-
Goldblatt, N.1
Leibowitz, M.2
Lo, W.3
-
46
-
-
0003519487
-
-
Marcel Dekker, New York First Edition, Chapter 4
-
R. Jenkins, R. W. Gould, Dale Gedcke, Quantitative X-Ray Spectrometry, Marcel Dekker, New York, 1981, First Edition, Chapter 4.
-
(1981)
Quantitative X-Ray Spectrometry
-
-
Jenkins, R.1
Gould, R.W.2
Gedcke, D.3
-
47
-
-
0027071420
-
Three dimensional effects of latchup turn-on CMOS and forward biased n+ diode measured by photoemissions
-
March
-
T. Ohzone, and H. Iwata, "Three dimensional effects of latchup turn-on CMOS and Forward Biased n+ diode measured by photoemissions," in Proceedings of IEEE International Conference on Microelectronic Test Structures, Vol. 5, March 1992, pp. 115-120.
-
(1992)
Proceedings of IEEE International Conference on Microelectronic Test Structures
, vol.5
, pp. 115-120
-
-
Ohzone, T.1
Iwata, H.2
-
49
-
-
0027067588
-
New failure analysis technique of ULS1 circuits using photon emission methods
-
March
-
Y. Uraoka, I. Miyanaga, T. Maeda, and K. Tsuji, "New Failure Analysis Technique of ULS1 Circuits Using Photon Emission Methods," in Proceedings of IEEE International Conference on Microelectronic Test Structures, Vol. 5, March 1992, pp. 100-106.
-
(1992)
Proceedings of IEEE International Conference on Microelectronic Test Structures
, vol.5
, pp. 100-106
-
-
Uraoka, Y.1
Miyanaga, I.2
Maeda, T.3
Tsuji, K.4
-
50
-
-
0037634701
-
New observance and analysis of various guard ring structures on latchup hardness by backside photoemission image
-
Latchup Session April
-
S. Liao et al., "New Observance and Analysis of Various Guard Ring Structures on Latchup Hardness by Backside Photoemission Image", Latchup Session, in Proceedings of International Reliablity Physics Symposium, April 2003.
-
(2003)
Proceedings of International Reliablity Physics Symposium
-
-
Liao, S.1
-
51
-
-
0037509749
-
A new I/O signal latchup phenomenon in voltage tolerance ESD protection circuits with PCI application
-
Latchup Session April
-
J. Salcedo et al., "A New I/O Signal Latchup Phenomenon in Voltage Tolerance ESD Protection Circuits With PCI Application," Latchup Session, in Proceedings of the International Reliablity Physics Symposium, April 2003.
-
(2003)
Proceedings of the International Reliablity Physics Symposium
-
-
Salcedo, J.1
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