Latchup in CMOS technology

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1998, Pages 269-278

  Hargrove, M J ^a   Voldman, S ^a   Gauthier, R ^a   Brown, J ^a   Duncan, K ^a   Craig, W ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC INVERTERS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; SURFACE PHENOMENA;

LATCHUP PHENOMENA;

CMOS INTEGRATED CIRCUITS;

EID: 0031707249     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/relphy.1998.670561     Document Type: Conference Paper

References (29)