Formal worst-case timing analysis of Ethernet topologies with strict-priority and AVB switching

7th IEEE International Symposium on Industrial Embedded Systems, SIES 2012 - Conference Proceedings

Volumn , Issue , 2012, Pages 1-10

  Diemer, Jonas ^a   Thiele, Daniel ^a   Ernst, Rolf ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION STANDARDS; CORNER CASE; CRITICAL ISSUES; DATA RATES; DISTRIBUTED EMBEDDED SYSTEM; FORMAL APPROACH; FRAME-TRANSFER; INDUSTRIAL AUTOMATION; IS COSTS; LOW-LATENCY COMMUNICATION; MULTIPLE DOMAINS; REAL TIME CONSTRAINTS; SAFETY CRITICAL APPLICATIONS; TIMING ANALYSIS; TIMING PROPERTIES; UPPER BOUND; WORST-CASE ANALYSIS;

EMBEDDED SYSTEMS; TOPOLOGY;

ETHERNET;

EID: 84871592337     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIES.2012.6356564     Document Type: Conference Paper

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