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Volumn , Issue , 2011, Pages 441-446

A 40 nm inverse-narrow-width-effect-aware sub-threshold standard cell library

Author keywords

Device Sizing; Inverse Narrow Width Effect; Sub threshold

Indexed keywords

COMPUTER AIDED DESIGN; DRAIN CURRENT; ELECTRIC POWER UTILIZATION; INVERSE PROBLEMS; THRESHOLD VOLTAGE;

EID: 80052678334     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024827     Document Type: Conference Paper
Times cited : (34)

References (11)
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  • 2
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  • 5
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    • A 180mV FFT Processor Using Subthreshold Circuit Techniques
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    • Alice Wang et al., "A 180mV FFT Processor Using Subthreshold Circuit Techniques," IEEE International Solid-State Circuits Conference (ISSCC), pp. 292-293, February 2004.
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    • Wang, A.1
  • 6
    • 0036539777 scopus 로고    scopus 로고
    • An anomalous device degradation of SOI narrow width devices caused by STI edge influence
    • Apr
    • Hyeokjae Lee et al., "An anomalous device degradation of SOI narrow width devices caused by STI edge influence," Electron Devices, IEEE Transactions on , vol.49, no.4, pp.605-612, Apr 2002
    • (2002) Electron Devices, IEEE Transactions on , vol.49 , Issue.4 , pp. 605-612
    • Lee, H.1
  • 7
    • 0023983720 scopus 로고
    • Inverse-narrow-width effects and small-geometry MOSFET threshold voltage model
    • Mar
    • Hsueh, K.K.-L. et al., "Inverse-narrow-width effects and small-geometry MOSFET threshold voltage model," Electron Devices, IEEE Transactions on , vol.35, no.3, pp.325-338, Mar 1988
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  • 9
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    • Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits
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    • Benton H. Calhoun et al., "Modeling and Sizing for Minimum Energy Operation in Sub-threshold Circuits," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, September 2005.
    • (2005) IEEE Journal of Solid-State Circuits , vol.40 , Issue.9 , pp. 1778-1786
    • Calhoun, B.H.1
  • 10
    • 34347222026 scopus 로고    scopus 로고
    • Subthreshold logical effort: A systematic framework for optimal subthreshold device sizing
    • vol., no.
    • Keane, J. et al., "Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing," Design Automation Conference, 2006 43rd ACM/IEEE , vol., no., pp.425-428.
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  • 11
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    • Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective
    • Feb
    • Gupta, S.K. et al., "Digital Computation in Subthreshold Region for Ultralow-Power Operation: A Device-Circuit-Architecture Codesign Perspective," Proceedings of the IEEE , vol.98, no.2, pp.160-190, Feb 2010
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.