Standard cell sizing for subthreshold operation

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 962-967

  Liu, Bo ^a,b   Ashouei, Maryam ^b   Huisken, Jos ^b   De Gyvez, Jose Pineda ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b HOLST CENTRE   (Netherlands)

Author keywords

process variation; standard cell library; subthreshold design; transistor sizing

Indexed keywords

LOG-NORMAL DISTRIBUTION; PROCESS VARIABILITY; PROCESS VARIATION; STANDARD CELL; STATISTICAL FORMULATION; SUB-THRESHOLD CURRENT; SUB-THRESHOLD DESIGN; SUBTHRESHOLD; SUBTHRESHOLD OPERATION; TRANSISTOR SIZING;

COMPUTER AIDED DESIGN; ENERGY UTILIZATION;

ELECTRIC BATTERIES;

EID: 84863541591     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228533     Document Type: Conference Paper

References (11)

1. Calhoun, B.H., Wang, A., Chandrakasan, A. 2005, "Modeling and sizing for minimum energy operation in subthreshold circuits", IEEE J. of Solid-State Circuits, pp. 1778-1786, 2005.
2. Keane, J., Hanyong Eom, Tae-Hyoung Kim, Sapatnekar, S., Kim, C. 2006, "Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing", 43rd ACM/IEEE Design Automation Conference, pp. 425-428, 2006.
3. Tae-Hyoung Kim, Hanyong Eom, Keane, J., Kim, C. 2006, "Utilizing reverse short channel effect for optimal subthreshold circuit design.", Int. Symp. Low Power Electronics and Design, pp. 127-130, 2006.
4. E. L. Crow and K. Shimizu, 1988, "Lognormal distributions: Theory and applications", CRC, 1988.
5. B. Zhai, S. Hanson, D. Blaauw, and D. Sylvester, 2005, "Analysis and mitigation of variability in subthreshold design", Int. Symp. Low Power Electronics and Design, pp. 20-25, 2005.
6. M. Pelgrom, A. Duinmaijer, A. Welbers, and A. P. G. Welbers, 1989, "Matching properties of MOS transistors", IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, 1989. (Pubitemid 20618569)
7. J. Kwong and A. P. Chandrakasan, 2006, "Variation-driven device sizing for minimum energy subthreshold circuits", Int. Symp. Low Power Electronics and Design. pp. 8-13, 2006.
8. H. Al-Hertani, D. Al-Khalili, and C. Rozon,2007, "A new subthreshold leakage model for NMOS transistor stacks", IEEE Northeast Workshop on Circuits and Systems, Montreal, QC, Canada, pp. 972-975, 2007.
9. L. Fenton, 1960, "The sum of log-normal probability distributions in scatter Transmission Systems", IRE Transactions onCommunications Systems, vol. 8, no. 1, pp. 57-67, 1960.
10. Y. Pu, J. Pineda de Gyvez, H. Corporaal, and Y. Ha, 2010, "An ultra low energy multi-standard JPEG co-processor in 65nm CMOS with sub/near threshold supply voltage", IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 668-680, 2010.
11. N. Lotze, J. Goppert, and Y. Manoli, 2010, "Timing modeling for digital sub- threshold circuits," in Design, Automation & Test in Europe Conference, pp. 299-302, 2010.