High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 182-183

  Seo, Jae Sun ^a   Ho, Ron ^b   Lexau, Jon ^b   Dayringer, Michael ^b   Sylvester, Dennis ^a   Blaauw, David ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ADAPTIVE FIR FILTERS; CAPACITIVE LOADS; CHIP INTEGRATION; CURRENT-MODE SIGNALING; ENERGY COST; HIGH BANDWIDTH; LOW ENERGIES; ON CHIPS; ON-CHIP SIGNALING; PRE-EMPHASIS; RANDOM DATA; RESISTIVE LOADS; SLEW RATE; TRADE OFF; VLSI SYSTEM; VOLTAGE SWINGS;

BANDWIDTH; FIR FILTERS; INTERSYMBOL INTERFERENCE; MICROPROCESSOR CHIPS; SIGNALING;

WIRE;

EID: 77952170789     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433993     Document Type: Conference Paper

References (8)

1. R. Ho, T. Ono, F. Liu, et al., "High-Speed and Low-Energy Capacitively-Driven On-Chip Wires," ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2007.
2. E. Mensink, D. Schinkel, E. Klumperink, et al., "A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-chip interconnects," ISSCC Dig. Tech. Papers, pp. 414-415, Feb. 2007.
3. N. Tzartzanis, and W. Walker, "Differential Current-Mode Sensing for Efficient On-Chip Global Signaling," IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2141-2147, Nov. 2005.
4. B. Kim, and V. Stojanovic, "A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 66-67, Feb. 2009.
5. D. Schinkel, E. Mensink, E. Klumperink, et al., "A 3-Gb/s/ch Transceiver for 10-mm Uninterrupted RC-limited Global On-Chip Interconnects," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 297-306, Jan. 2006.
6. N. Miura, H. Ishikuro, T. Sakurai, and T. Kuroda, "A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping," ISSCC Dig. Tech. Papers, pp. 358-359, Feb. 2007.
7. J. Bae, J.-Y. Kim, and H.-J. Yoo, "0.6pJ/b 3Gb/s/ch Transceiver in 0.18μm CMOS for 10mm On-Chip Interconnects," IEEE International Symposium on Circuits and Systems, pp. 2861-2864, May 2008.
8. R. Ho, B. Amrutur, K. Mai, et al., "Applications for On-Chip Samplers for Test and Measurement of Integrated Circuits," Symp. VLSI Circuits, pp. 138-139, Jun. 1998.