-
1
-
-
0034428118
-
System-level design: Orthogonalization of concerns and platformbased design
-
Dec.
-
K. Keutzer, A. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli, "System-level design: Orthogonalization of concerns and platformbased design," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19, no. 12, pp. 1523-1543, Dec. 2000.
-
(2000)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.19
, Issue.12
, pp. 1523-1543
-
-
Keutzer, K.1
Newton, A.2
Rabaey, J.3
Sangiovanni-Vincentelli, A.4
-
2
-
-
33744752126
-
Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design
-
Jun.
-
C. Erbas, S. Cerav-Erbas, and A. D. Pimentel, "Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design," IEEE Trans. Evol. Comput., vol. 10, no. 3, pp. 358-374, Jun. 2006.
-
(2006)
IEEE Trans. Evol. Comput.
, vol.10
, Issue.3
, pp. 358-374
-
-
Erbas, C.1
Cerav-Erbas, S.2
Pimentel, A.D.3
-
3
-
-
34547174070
-
Multi-objective design space exploration of embedded system
-
G. Palermo, C. Silvano, and V. Zaccaria, "Multi-objective design space exploration of embedded system," J. Embedded Comput., vol. 1, no. 3, pp. 305-316, 2006.
-
(2006)
J. Embedded Comput.
, vol.1
, Issue.3
, pp. 305-316
-
-
Palermo, G.1
Silvano, C.2
Zaccaria, V.3
-
4
-
-
77952945784
-
Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems
-
Jun.
-
F. Ferrandi, P. L. Lanzi, C. Pilato, D. Sciuto, and A. Tumeo, "Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 6, pp. 911-924, Jun. 2010.
-
(2010)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.29
, Issue.6
, pp. 911-924
-
-
Ferrandi, F.1
Lanzi, P.L.2
Pilato, C.3
Sciuto, D.4
Tumeo, A.5
-
5
-
-
70450247054
-
ReSPIR: A response surfacebased Pareto iterative refinement for application-specific design space exploration
-
Dec.
-
G. Palermo, C. Silvano, and V. Zaccaria, "ReSPIR: A response surfacebased Pareto iterative refinement for application-specific design space exploration," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 28, no. 12, pp. 1816-1829, Dec. 2009.
-
(2009)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.28
, Issue.12
, pp. 1816-1829
-
-
Palermo, G.1
Silvano, C.2
Zaccaria, V.3
-
6
-
-
84858315095
-
Boosting design space explorations with existing or automatically learned knowledge
-
J. Schmitt, Ed., Berlin, Germany: Springer
-
R. Jahr, H. Calborean, L. Vintan, and T. Ungerer, "Boosting design space explorations with existing or automatically learned knowledge," in Measurement, Modelling, and Evaluation of Computing Systems and Dependability and Fault Tolerance (Lecture Notes in Computer Science 7201), J. Schmitt, Ed., Berlin, Germany: Springer, 2012, pp. 221-235.
-
(2012)
Measurement, Modelling, and Evaluation of Computing Systems and Dependability and Fault Tolerance (Lecture Notes in Computer Science 7201)
, pp. 221-235
-
-
Jahr, R.1
Calborean, H.2
Vintan, L.3
Ungerer, T.4
-
7
-
-
33644879118
-
-
(Jan.). [Online]
-
J. Renau et al., (Jan. 2005). SESC Simulator. [Online]. Available: http://sesc.sourceforge.net
-
(2005)
SESC Simulator
-
-
Renau, J.1
-
8
-
-
51549109604
-
Parallelizing CAD: A timely research agenda for EDA
-
Anaheim, CA, USA, Jun.
-
B. Catanzaro, K. Keutzer, and B.-Y. Su, "Parallelizing CAD: A timely research agenda for EDA," in Proc. 45th ACM/IEEE Design Autom. Conf. (DAC), Anaheim, CA, USA, Jun. 2008, pp. 12-17.
-
(2008)
Proc. 45th ACM/IEEE Design Autom. Conf. (DAC)
, pp. 12-17
-
-
Catanzaro, B.1
Keutzer, K.2
Su, B.-Y.3
-
9
-
-
84898687555
-
Developing parallel EDA tools [the last byte]
-
Feb.
-
L. Stok, "Developing parallel EDA tools [the last byte]," IEEE Des. Test, vol. 30, no. 1, pp. 65-66, Feb. 2013.
-
(2013)
IEEE Des. Test
, vol.30
, Issue.1
, pp. 65-66
-
-
Stok, L.1
-
10
-
-
79960665878
-
A special section on multicore parallel CAD: Algorithm design and programming
-
Jun.
-
K. Keutzer, P. Li, L. Shang, and H. Zhou, "A special section on multicore parallel CAD: Algorithm design and programming," ACM Trans. Design Autom. Electron. Syst., vol. 16, no. 3, pp. 21:1-21:2, Jun. 2011.
-
(2011)
ACM Trans. Design Autom. Electron. Syst.
, vol.16
, Issue.3
, pp. 1-2
-
-
Keutzer, K.1
Li, P.2
Shang, L.3
Zhou, H.4
-
11
-
-
84860271429
-
OSCAR: An optimization methodology exploiting spatial correlation in multicore design spaces
-
May
-
G. Mariani, G. Palermo, V. Zaccaria, and C. Silvano, "OSCAR: An optimization methodology exploiting spatial correlation in multicore design spaces," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 31, no. 5, pp. 740-753, May 2012.
-
(2012)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.
, vol.31
, Issue.5
, pp. 740-753
-
-
Mariani, G.1
Palermo, G.2
Zaccaria, V.3
Silvano, C.4
-
12
-
-
70350618463
-
Accurate and efficient processor performance prediction via regression tree based modeling
-
B. Li, L. Peng, and B. Ramadass, "Accurate and efficient processor performance prediction via regression tree based modeling," J. Syst. Archit., vol. 55, nos. 10-12, pp. 457-467, 2009.
-
(2009)
J. Syst. Archit.
, vol.55
, Issue.10-12
, pp. 457-467
-
-
Li, B.1
Peng, L.2
Ramadass, B.3
-
13
-
-
34248506586
-
Efficient design space exploration for application specific systems-on-A-chip
-
G. Ascia, V. Catania, A. G. D. Nuovo, M. Palesi, and D. Patti, "Efficient design space exploration for application specific systems-on-a-chip," J. Syst. Archit., vol. 53, no. 10, pp. 733-750, 2007.
-
(2007)
J. Syst. Archit.
, vol.53
, Issue.10
, pp. 733-750
-
-
Ascia, G.1
Catania, V.2
Nuovo, A.G.D.3
Palesi, M.4
Patti, D.5
-
14
-
-
83155173614
-
Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation
-
Seatle, WA, USA, Nov.
-
T. Carlson, W. Heirman, and L. Eeckhout, "Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation," in Proc. Int. Conf. High Perform. Comput. Netw. Storage Anal., Seatle, WA, USA, Nov. 2011, pp. 1-12.
-
(2011)
Proc. Int. Conf. High Perform. Comput. Netw. Storage Anal.
, pp. 1-12
-
-
Carlson, T.1
Heirman, W.2
Eeckhout, L.3
-
15
-
-
77952555923
-
SlackSim: A platform for parallel simulations of CMPs on CMPs
-
Jul.
-
J. Chen, M. Annavaram, and M. Dubois, "SlackSim: A platform for parallel simulations of CMPs on CMPs," SIGARCH Comput. Archit. News, vol. 37, no. 2, pp. 20-29, Jul. 2009.
-
(2009)
SIGARCH Comput. Archit. News
, vol.37
, Issue.2
, pp. 20-29
-
-
Chen, J.1
Annavaram, M.2
Dubois, M.3
-
16
-
-
80052679723
-
MARSS: A full system simulator for multicore x86 CPUs
-
New York, NY, USA, Jun.
-
A. Patel, F. Afram, S. Chen, and K. Ghose, "MARSS: A full system simulator for multicore x86 CPUs," in Proc. 48th ACM/EDAC/IEEE Design Autom. Conf. (DAC), New York, NY, USA, Jun. 2011, pp. 1050-1055.
-
(2011)
Proc. 48th ACM/EDAC/IEEE Design Autom. Conf. (DAC)
, pp. 1050-1055
-
-
Patel, A.1
Afram, F.2
Chen, S.3
Ghose, K.4
-
17
-
-
0029179077
-
The SPLASH-2 programs: Characterization and methodological considerations
-
Santa Margherita Ligure, Italy
-
S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, "The SPLASH-2 programs: Characterization and methodological considerations," in Proc. 22nd Annu. Int. Comput. Archit. Symp., Santa Margherita Ligure, Italy, 1995, pp. 24-36.
-
(1995)
Proc. 22nd Annu. Int. Comput. Archit. Symp.
, pp. 24-36
-
-
Woo, S.C.1
Ohara, M.2
Torrie, E.3
Singh, J.P.4
Gupta, A.5
-
18
-
-
84903832106
-
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling
-
Mar.
-
G. Mariani, G. Palermo, V. Zaccaria, and C. Silvano, "DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling," in Proc. Design Autom. Test Europe Conf. Exhibit. (DATE), Mar. 2014, pp. 1-4.
-
(2014)
Proc. Design Autom. Test Europe Conf. Exhibit. (DATE)
, pp. 1-4
-
-
Mariani, G.1
Palermo, G.2
Zaccaria, V.3
Silvano, C.4
-
19
-
-
80053303144
-
-
New York, NY, USA: Springer
-
C. Silvano, W. Fornaciari, and E. Villar, Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach. New York, NY, USA: Springer, 2011.
-
(2011)
Multi-objective Design Space Exploration of Multiprocessor SoC Architectures: The MULTICUBE Approach
-
-
Silvano, C.1
Fornaciari, W.2
Villar, E.3
-
21
-
-
84897007856
-
A comparative evaluation of multiobjective exploration algorithms for high-level design
-
Mar.
-
J. Panerati and G. Beltrame, "A comparative evaluation of multiobjective exploration algorithms for high-level design," ACM Trans. Design Autom. Electron. Syst., vol. 19, pp. 15:1-15:22, Mar. 2014.
-
(2014)
ACM Trans. Design Autom. Electron. Syst.
, vol.19
, pp. 1-22
-
-
Panerati, J.1
Beltrame, G.2
-
22
-
-
34547224724
-
Overview of the MPSoC design challenge
-
New York, NY, USA
-
G. Martin, "Overview of the MPSoC design challenge," in Proc. 43rd Annu. Design Autom. Conf. (DAC), New York, NY, USA, 2006, pp. 274-279.
-
(2006)
Proc. 43rd Annu. Design Autom. Conf. (DAC)
, pp. 274-279
-
-
Martin, G.1
-
23
-
-
70350746332
-
A design space exploration methodology supporting run-time resource management for multi-processor systems-on-chip
-
San Francisco, CA, USA
-
G. Mariani, G. Palermo, C. Silvano, and V. Zaccaria, "A design space exploration methodology supporting run-time resource management for multi-processor systems-on-chip," in Proc. IEEE 7th Symp. Appl. Specific Process. (SASP), San Francisco, CA, USA, 2009, pp. 21-28.
-
(2009)
Proc. IEEE 7th Symp. Appl. Specific Process. (SASP)
, pp. 21-28
-
-
Mariani, G.1
Palermo, G.2
Silvano, C.3
Zaccaria, V.4
-
24
-
-
84862093125
-
Design space pruning through hybrid analysis in system-level design space exploration
-
Dresden, Germany
-
R. Piscitelli and A. Pimentel, "Design space pruning through hybrid analysis in system-level design space exploration," in Proc. Design Autom. Test Europe Conf. Exhibit. (DATE), Dresden, Germany, 2012, pp. 781-786.
-
(2012)
Proc. Design Autom. Test Europe Conf. Exhibit. (DATE)
, pp. 781-786
-
-
Piscitelli, R.1
Pimentel, A.2
-
25
-
-
57649239578
-
Discrete particle swarm optimization for multi-objective design space exploration
-
Parma, Italy
-
G. Palermo, C. Silvano, and V. Zaccaria, "Discrete particle swarm optimization for multi-objective design space exploration," in Proc. 11th EUROMICRO Conf. Digit. Syst. Design Archit. Methods Tools (DSD), Parma, Italy, 2008, pp. 641-644.
-
(2008)
Proc. 11th EUROMICRO Conf. Digit. Syst. Design Archit. Methods Tools (DSD)
, pp. 641-644
-
-
Palermo, G.1
Silvano, C.2
Zaccaria, V.3
-
26
-
-
72149129159
-
Mapping pipelined applications onto heterogeneous embedded systems: A Bayesian optimization algorithm based approach
-
New York, NY, USA
-
A. Tumeo et al., "Mapping pipelined applications onto heterogeneous embedded systems: A Bayesian optimization algorithm based approach," in Proc. 7th IEEE/ACM Int. Conf. Hardw./Softw. Codesign Syst. Synth. (CODES+ISSS), New York, NY, USA, 2009, pp. 443-452.
-
(2009)
Proc. 7th IEEE/ACM Int. Conf. Hardw./Softw. Codesign Syst. Synth. (CODES+ISSS)
, pp. 443-452
-
-
Tumeo, A.1
-
27
-
-
77955860548
-
Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation
-
New York, NY, USA
-
M. Ceriani, F. Ferrandi, P. L. Lanzi, D. Sciuto, and A. Tumeo, "Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation," in Proc. ACM 12th Annu. Conf. Genet. Evol. Comput. (GECCO), New York, NY, USA, 2010, pp. 1267-1274.
-
(2010)
Proc. ACM 12th Annu. Conf. Genet. Evol. Comput. (GECCO)
, pp. 1267-1274
-
-
Ceriani, M.1
Ferrandi, F.2
Lanzi, P.L.3
Sciuto, D.4
Tumeo, A.5
-
28
-
-
84879851819
-
On learning-based methods for design-space exploration with high-level synthesis
-
Austin, TX, USA, May
-
H.-Y. Liu and L. Carloni, "On learning-based methods for design-space exploration with high-level synthesis," in Proc. 50th ACM/EDAC/IEEE Design Autom. Conf. (DAC), Austin, TX, USA, May 2013, pp. 1-7.
-
(2013)
Proc. 50th ACM/EDAC/IEEE Design Autom. Conf. (DAC)
, pp. 1-7
-
-
Liu, H.-Y.1
Carloni, L.2
-
29
-
-
34548301455
-
Soft-core processor customization using the design of experiments paradigm
-
Nice, France
-
D. Sheldon, F. Vahid, and S. Lonardi, "Soft-core processor customization using the design of experiments paradigm," in Proc. Conf. Design Autom. Test Europe (DATE), Nice, France, 2007, pp. 821-826.
-
(2007)
Proc. Conf. Design Autom. Test Europe (DATE)
, pp. 821-826
-
-
Sheldon, D.1
Vahid, F.2
Lonardi, S.3
-
30
-
-
0038346244
-
SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling
-
New York, NY, USA
-
R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe, "SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling," in Proc. ACM 30th Annu. Int. Symp. Comput. Archit. (ISCA), New York, NY, USA, 2003, pp. 84-97.
-
(2003)
Proc. ACM 30th Annu. Int. Symp. Comput. Archit. (ISCA)
, pp. 84-97
-
-
Wunderlich, R.E.1
Wenisch, T.F.2
Falsafi, B.3
Hoe, J.C.4
-
31
-
-
27144551353
-
Using SimPoint for accurate and efficient simulation
-
E. Perelman, G. Hamerly, M. V. Biesbrouck, T. Sherwood, and B. Calder, "Using SimPoint for accurate and efficient simulation," ACM SIGMETRICS Perform. Eval. Rev., vol. 31, no. 1, pp. 318-319, 2003.
-
(2003)
ACM SIGMETRICS Perform. Eval. Rev.
, vol.31
, Issue.1
, pp. 318-319
-
-
Perelman, E.1
Hamerly, G.2
Biesbrouck, M.V.3
Sherwood, T.4
Calder, B.5
-
32
-
-
33947713690
-
Efficient sampling startup for SimPoint
-
Jul.
-
M. V. Biesbrouck, B. Calder, and L. Eeckhout, "Efficient sampling startup for SimPoint," IEEE Micro, vol. 26, no. 4, pp. 32-42, Jul. 2006.
-
(2006)
IEEE Micro
, vol.26
, Issue.4
, pp. 32-42
-
-
Biesbrouck, M.V.1
Calder, B.2
Eeckhout, L.3
-
33
-
-
77952575783
-
How to simulate 1000 cores
-
Jul.
-
M. Monchiero, J. H. Ahn, A. Falcón, D. Ortega, and P. Faraboschi, "How to simulate 1000 cores," SIGARCH Comput. Archit. News, vol. 37, pp. 10-19, Jul. 2009.
-
(2009)
SIGARCH Comput. Archit. News
, vol.37
, pp. 10-19
-
-
Monchiero, M.1
Ahn, J.H.2
Falcón, A.3
Ortega, D.4
Faraboschi, P.5
-
34
-
-
84869485152
-
Fast and accurate simulation of the Cray XMT multithreaded supercomputer
-
Dec.
-
O. Villa, A. Tumeo, S. Secchi, and J. B. Manzano, "Fast and accurate simulation of the Cray XMT multithreaded supercomputer," IEEE Trans. Parallel Distrib. Syst., vol. 23, no. 12, pp. 2266-2279, Dec. 2012.
-
(2012)
IEEE Trans. Parallel Distrib. Syst.
, vol.23
, Issue.12
, pp. 2266-2279
-
-
Villa, O.1
Tumeo, A.2
Secchi, S.3
Manzano, J.B.4
-
35
-
-
84859962723
-
Parallel simulation of mixedabstraction SystemC models on GPUs and multicore CPUs
-
Sydney, NSW, Australia, Jan.
-
R. Sinha, A. Prakash, and H. Patel, "Parallel simulation of mixedabstraction SystemC models on GPUs and multicore CPUs," in Proc. 2012 17th Asia South Pac. Design Autom. Conf. (ASP-DAC), Sydney, NSW, Australia, Jan. 2012, pp. 455-460.
-
(2012)
Proc. 2012 17th Asia South Pac. Design Autom. Conf. (ASP-DAC)
, pp. 455-460
-
-
Sinha, R.1
Prakash, A.2
Patel, H.3
-
36
-
-
47849123249
-
Using predictive modeling for cross-program design space exploration in multicore systems
-
Brasov, Romania, Sep.
-
S. Khan, P. Xekalakis, J. Cavazos, and M. Cintra, "Using predictive modeling for cross-program design space exploration in multicore systems," in Proc. 16th Int. Conf. Parallel Archit. Compilation Tech. (PACT), Brasov, Romania, Sep. 2007, pp. 327-338.
-
(2007)
Proc. 16th Int. Conf. Parallel Archit. Compilation Tech. (PACT)
, pp. 327-338
-
-
Khan, S.1
Xekalakis, P.2
Cavazos, J.3
Cintra, M.4
-
37
-
-
51549114087
-
Predictive design space exploration using genetically programmed response surfaces
-
New York, NY, USA
-
H. Cook and K. Skadron, "Predictive design space exploration using genetically programmed response surfaces," in Proc. ACM 45th Annu. Design Autom. Conf. (DAC), New York, NY, USA, 2008, pp. 960-965.
-
(2008)
Proc. ACM 45th Annu. Design Autom. Conf. (DAC)
, pp. 960-965
-
-
Cook, H.1
Skadron, K.2
-
38
-
-
33748863916
-
Construction and use of linear regression models for processor performance analysis
-
Austin, TX, USA
-
P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil, "Construction and use of linear regression models for processor performance analysis," in Proc. Symp. High Perform. Comput. Archit., Austin, TX, USA, 2006, pp. 99-108.
-
(2006)
Proc. Symp. High Perform. Comput. Archit.
, pp. 99-108
-
-
Joseph, P.J.1
Vaswani, K.2
Thazhuthaveetil, M.J.3
-
39
-
-
34548333834
-
A predictive performance model for superscalar processors
-
Washington, DC, USA
-
P. J. Joseph, K. Vaswani, and M. J. Thazhuthaveetil, "A predictive performance model for superscalar processors," in Proc. 39th Annu. IEEE/ACM Int. Symp. Microarchit. (MICRO), Washington, DC, USA, 2006, pp. 161-170.
-
(2006)
Proc. 39th Annu. IEEE/ACM Int. Symp. Microarchit. (MICRO)
, pp. 161-170
-
-
Joseph, P.J.1
Vaswani, K.2
Thazhuthaveetil, M.J.3
-
40
-
-
66749097272
-
Efficient architectural design space exploration via predictive modeling
-
E. Ipek et al., "Efficient architectural design space exploration via predictive modeling," ACM Trans. Archit. Code Optim., vol. 4, no. 4, pp. 1-34, 2008.
-
(2008)
ACM Trans. Archit. Code Optim.
, vol.4
, Issue.4
, pp. 1-34
-
-
Ipek, E.1
-
41
-
-
84870233156
-
Microarchitectural design space exploration made fast
-
Q. Guo, T. Chen, Y. Chen, L. Li, and W. Hu, "Microarchitectural design space exploration made fast," Microprocess. Microsyst., vol. 37, no. 1, pp. 41-51, 2013.
-
(2013)
Microprocess. Microsyst.
, vol.37
, Issue.1
, pp. 41-51
-
-
Guo, Q.1
Chen, T.2
Chen, Y.3
Li, L.4
Hu, W.5
-
42
-
-
84866340251
-
Smart' design space sampling to predict Pareto-optimal solutions
-
New York, NY, USA
-
M. Zuluaga, A. Krause, P. Milder, and M. Püschel, "'Smart' design space sampling to predict Pareto-optimal solutions," in Proc. 13th ACM SIGPLAN/SIGBED Int. Conf. Lang. Compilers Tools Theory Embedded Syst. (LCTES), New York, NY, USA, 2012, pp. 119-128.
-
(2012)
Proc. 13th ACM SIGPLAN/SIGBED Int. Conf. Lang. Compilers Tools Theory Embedded Syst. (LCTES)
, pp. 119-128
-
-
Zuluaga, M.1
Krause, A.2
Milder, P.3
Püschel, M.4
-
43
-
-
77956212269
-
A correlation-based design space exploration methodology for multi-processor systems-on-chip
-
Anaheim, CA, USA
-
G. Mariani et al., "A correlation-based design space exploration methodology for multi-processor systems-on-chip," in Proc. 47th ACM/IEEE Design Autom. Conf. (DAC), Anaheim, CA, USA, 2010, pp. 120-125.
-
(2010)
Proc. 47th ACM/IEEE Design Autom. Conf. (DAC)
, pp. 120-125
-
-
Mariani, G.1
-
44
-
-
70449435468
-
A parallel genetic algorithm in multi-objective optimization
-
Guilin, China, Jun.
-
W. Zhi-xin and J. Gang, "A parallel genetic algorithm in multi-objective optimization," in Proc. Control Decis. Conf. (CCDC) Chinese, Guilin, China, Jun. 2009, pp. 3497-3501.
-
(2009)
Proc. Control Decis. Conf. (CCDC) Chinese
, pp. 3497-3501
-
-
Zhi-Xin, W.1
Gang, J.2
-
45
-
-
14244258507
-
Distributed computing in practice: The Condor experience
-
D. Thain, T. Tannenbaum, and M. Livny, "Distributed computing in practice: The Condor experience," Concurr. Pract. Exp., vol. 17, nos. 2-4, pp. 323-356, 2005.
-
(2005)
Concurr. Pract. Exp.
, vol.17
, Issue.2-4
, pp. 323-356
-
-
Thain, D.1
Tannenbaum, T.2
Livny, M.3
-
46
-
-
84877687488
-
A multi-objective auto-tuning framework for parallel codes
-
Los Alamitos, CA, USA
-
H. Jordan et al., "A multi-objective auto-tuning framework for parallel codes," in Proc. Int. Conf. High Perform. Comput. Netw. Storage Anal., Los Alamitos, CA, USA, 2012, pp. 10:1-10:12.
-
(2012)
Proc. Int. Conf. High Perform. Comput. Netw. Storage Anal.
, pp. 1-12
-
-
Jordan, H.1
-
47
-
-
77956875401
-
A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems
-
Oct.
-
J. L. Risco-Martín, D. Atienza, J. Manuel Colmenar, and O. Garnica, "A parallel evolutionary algorithm to optimize dynamic memory managers in embedded systems," J. Parallel Comput., vol. 36, pp. 572-590, Oct. 2010.
-
(2010)
J. Parallel Comput.
, vol.36
, pp. 572-590
-
-
Risco-Martín, J.L.1
Atienza, D.2
Manuel Colmenar, J.3
Garnica, O.4
-
48
-
-
0004068617
-
A parallel genetic algorithm for multiobjective microprocessor design
-
San Francisco, CA, USA
-
T. Stanley and T. Mudge, "A parallel genetic algorithm for multiobjective microprocessor design," in Proc. 6th Int. Conf. Genet. Algorithms, San Francisco, CA, USA, 1995, pp. 597-604.
-
(1995)
Proc. 6th Int. Conf. Genet. Algorithms
, pp. 597-604
-
-
Stanley, T.1
Mudge, T.2
-
49
-
-
84880272089
-
ESESC: A fast multicore simulator using time-based sampling
-
Washington, DC, USA
-
E. K. Ardestani and J. Renau, "ESESC: A fast multicore simulator using time-based sampling," in Proc. 2013 IEEE 19th Int. Symp. High Perform. Comput. Archit. (HPCA), Washington, DC, USA, pp. 448-459.
-
Proc. 2013 IEEE 19th Int. Symp. High Perform. Comput. Archit. (HPCA)
, pp. 448-459
-
-
Ardestani, E.K.1
Renau, J.2
-
50
-
-
57349180474
-
An EDA based on local Markov property and Gibbs sampling
-
New York, NY, USA
-
S. Shakya and R. Santana, "An EDA based on local Markov property and Gibbs sampling," in Proc. 10th Annu. Conf. Genet. Evol. Comput. (GECCO), New York, NY, USA, 2008, pp. 475-476.
-
(2008)
Proc. 10th Annu. Conf. Genet. Evol. Comput. (GECCO)
, pp. 475-476
-
-
Shakya, S.1
Santana, R.2
-
51
-
-
72749127950
-
-
Dept. Comput. Sci. Artif. Intell., Univ. Basque Country, Leioa, Spain, Tech. Rep., Feb.
-
R. Santana et al., "MATEDA: A suite of EDA programs in Matlab," Dept. Comput. Sci. Artif. Intell., Univ. Basque Country, Leioa, Spain, Tech. Rep. EHU-KZAA-IK-2/09, Feb. 2009.
-
(2009)
MATEDA: A Suite of EDA Programs in Matlab
-
-
Santana, R.1
-
53
-
-
35048844152
-
Fitness inheritance in the Bayesian optimization algorithm
-
Berlin, Germany: Springer
-
M. Pelikan and K. Sastry, "Fitness inheritance in the Bayesian optimization algorithm," in Genet. Evol. Comput. (Lecture Notes in Computer Science 3103), Berlin, Germany: Springer, 2004, pp. 48-59.
-
(2004)
Genet. Evol. Comput. (Lecture Notes in Computer Science 3103)
, pp. 48-59
-
-
Pelikan, M.1
Sastry, K.2
-
54
-
-
84901430753
-
A critical survey of performance indices for multi-objective optimization
-
Canberra, ACT, Australia
-
T. Okabe, Y. Jin, and B. Sendhoff, "A critical survey of performance indices for multi-objective optimization," in Proc. IEEE Congr. Evol. Comput., Canberra, ACT, Australia, 2003, pp. 878-885.
-
(2003)
Proc. IEEE Congr. Evol. Comput.
, pp. 878-885
-
-
Okabe, T.1
Jin, Y.2
Sendhoff, B.3
-
55
-
-
0036530772
-
A fast and elitist multiobjective genetic algorithm: NSGA-II
-
Apr.
-
K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, "A fast and elitist multiobjective genetic algorithm: NSGA-II," IEEE Trans. Evol. Comput., vol. 6, no. 2, pp. 182-197, Apr. 2002.
-
(2002)
IEEE Trans. Evol. Comput.
, vol.6
, Issue.2
, pp. 182-197
-
-
Deb, K.1
Pratap, A.2
Agarwal, S.3
Meyarivan, T.4
-
56
-
-
0034871145
-
Managing approximate models in evolutionary aerodynamic design optimization
-
Seoul, Korea
-
Y. Jin, M. Olhofer, and B. Sendhoff, "Managing approximate models in evolutionary aerodynamic design optimization," in Proc. Congr. Evol. Comput., vol. 1. Seoul, Korea, 2001, pp. 592-599.
-
(2001)
Proc. Congr. Evol. Comput.
, vol.1
, pp. 592-599
-
-
Jin, Y.1
Olhofer, M.2
Sendhoff, B.3
-
57
-
-
84921462351
-
Using chip multithreading to speed up scenario-based design space exploration: A case study
-
New York, NY, USA
-
P. van Stralen and A. D. Pimentel, "Using chip multithreading to speed up scenario-based design space exploration: A case study," in Proc. ACM 6th Workshop Rapid Simulat. Perform. Eval. Methods Tools (RAPIDO), New York, NY, USA, 2014, pp. 1:1-1:7.
-
(2014)
Proc. ACM 6th Workshop Rapid Simulat. Perform. Eval. Methods Tools (RAPIDO)
, pp. 1-7
-
-
Van Stralen, P.1
Pimentel, A.D.2
-
58
-
-
84885674058
-
Design-space exploration and runtime resource management for multicores
-
Sep.
-
G. Mariani, G. Palermo, V. Zaccaria, and C. Silvano, "Design-space exploration and runtime resource management for multicores," ACM Trans. Embedded Comput. Syst., vol. 13, pp. 20:1-20:27, Sep. 2013.
-
(2013)
ACM Trans. Embedded Comput. Syst.
, vol.13
, pp. 1-27
-
-
Mariani, G.1
Palermo, G.2
Zaccaria, V.3
Silvano, C.4
-
59
-
-
84901420886
-
Scalable multi-objective optimization test problems
-
Honolulu, HI, USA
-
K. Deb, L. Thiele, M. Laumanns, and E. Zitzler, "Scalable multi-objective optimization test problems," in Proc. Congr. Evol. Comput. (CEC), vol. 1. Honolulu, HI, USA, 2002, pp. 825-830.
-
(2002)
Proc. Congr. Evol. Comput. (CEC)
, vol.1
, pp. 825-830
-
-
Deb, K.1
Thiele, L.2
Laumanns, M.3
Zitzler, E.4
|