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Volumn 28, Issue 12, 2009, Pages 1816-1829

ReSPIR: A response surface-based pareto iterative refinement for application-specific design space exploration

Author keywords

Application specific processors; Chip multiprocessors; Design space exploration

Indexed keywords

APPLICATION SPECIFIC PROCESSORS; APPLICATION-SPECIFIC; ARCHITECTURE CONFIGURATION; CHIP MULTIPROCESSOR; CUSTOMIZABLE; DESIGN SPACE EXPLORATION; FEASIBLE SOLUTION; FIGURES OF MERITS; HEURISTIC TECHNIQUES; ITERATIVE REFINEMENT; MULTI-OBJECTIVE OPTIMIZATION PROBLEM; MULTIPLE CONSTRAINT; MULTIPROCESSOR SYSTEMS ON CHIPS; ON-CHIP MULTIPROCESSOR; PARETO FRONT; RESPONSE SURFACE; RESPONSE SURFACE MODELING; SHARED MEMORIES; SIMULATION-BASED; SYSTEM LEVELS; TARGET DESIGN; TRADE OFF;

EID: 70450247054     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2009.2028681     Document Type: Article
Times cited : (114)

References (40)
  • 5
    • 34547174070 scopus 로고    scopus 로고
    • Multi-objective design space exploration of embedded system
    • G. Palermo, C. Silvano, and V. Zaccaria, "Multi-objective design space exploration of embedded system," J. Embed. Comput., vol.1, no.3, pp. 305-316, 2006.
    • (2006) J. Embed. Comput. , vol.1 , Issue.3 , pp. 305-316
    • Palermo, G.1    Silvano, C.2    Zaccaria, V.3
  • 6
    • 34248506586 scopus 로고    scopus 로고
    • Efficient design space exploration for application specific systems-on-a-chip
    • Oct.
    • G. Ascia, V. Catania, A. G. Di Nuovo, M. Palesi, and D. Patti, "Efficient design space exploration for application specific systems-on-a-chip," J. Syst. Archit., vol.53, no.10, pp. 733-750, Oct. 2007.
    • (2007) J. Syst. Archit. , vol.53 , Issue.10 , pp. 733-750
    • Ascia, G.1    Catania, V.2    Di Nuovo, A.G.3    Palesi, M.4    Patti, D.5
  • 9
    • 34547288276 scopus 로고    scopus 로고
    • Accurate and efficient regression modeling for microarchitectural performance and power prediction
    • B. C. Lee and D. M. Brooks, "Accurate and efficient regression modeling for microarchitectural performance and power prediction," in Proc. 12th Int. Conf. Archit. Support Program. Lang. Oper. Syst., 2006, pp. 185-194.
    • (2006) Proc. 12th Int. Conf. Archit. Support Program. Lang. Oper. Syst. , pp. 185-194
    • Lee, B.C.1    Brooks, D.M.2
  • 11
    • 34548301455 scopus 로고    scopus 로고
    • Soft-core processor customization using the design of experiments paradigm
    • D. Sheldon, F. Vahid, and S. Lonardi, "Soft-core processor customization using the design of experiments paradigm," in Proc. Conf. DATE, 2007, pp. 821-826.
    • (2007) Proc. Conf. DATE , pp. 821-826
    • Sheldon, D.1    Vahid, F.2    Lonardi, S.3
  • 12
    • 33749057743 scopus 로고    scopus 로고
    • A statistically rigorous approach for improving simulation methodology
    • J. J. Yi, D. J. Lilja, and D. M. Hawkins, "A statistically rigorous approach for improving simulation methodology," in Proc. 9th Int. Symp. HPCA, 2003, pp. 281-291.
    • (2003) Proc. 9th Int. Symp. HPCA , pp. 281-291
    • Yi, J.J.1    Lilja, D.J.2    Hawkins, D.M.3
  • 13
    • 58049192635 scopus 로고    scopus 로고
    • An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods
    • G. Palermo, C. Silvano, and V. Zaccaria, "An efficient design space exploration methodology for multiprocessor SoC architectures based on response surface methods," in Proc. IC-SAMOS, 2008, pp. 150-157.
    • (2008) Proc. IC-SAMOS , pp. 150-157
    • Palermo, G.1    Silvano, C.2    Zaccaria, V.3
  • 14
    • 52349122601 scopus 로고    scopus 로고
    • An efficient design space exploration methodology for on-chip multiprocessors subject to applicationspecific constraints
    • G. Palermo, C. Silvano, and V. Zaccaria, "An efficient design space exploration methodology for on-chip multiprocessors subject to applicationspecific constraints," in Proc. SASP, 2008, pp. 75-82.
    • (2008) Proc. SASP , pp. 75-82
    • Palermo, G.1    Silvano, C.2    Zaccaria, V.3
  • 15
    • 70450252323 scopus 로고    scopus 로고
    • [Online]. Available
    • Synopsys, IP-Based Design-Core Consultant. [Online]. Available: www.synopsys.com/products/designware/core-consultant.html
    • IP-Based Design-Core Consultant
  • 17
    • 84901430753 scopus 로고    scopus 로고
    • A critical survey of performance indices for multi-objective optimization
    • T. Okabe, Y. Jin, and B. Sendhoff, "A critical survey of performance indices for multi-objective optimization," in Proc. IEEE Congr. Evol. Comput., 2003, pp. 878-885.
    • (2003) Proc. IEEE Congr. Evol. Comput. , pp. 878-885
    • Okabe, T.1    Jin, Y.2    Sendhoff, B.3
  • 18
    • 85018104842 scopus 로고    scopus 로고
    • Pareto simulated annealing-A metaheuristic technique for multiple-objective combinatorial optimization
    • Jan.
    • A. Jaszkiewicz and P. Czyzak, "Pareto simulated annealing-A metaheuristic technique for multiple-objective combinatorial optimization," J. Multi-Criteria Decis. Anal., vol.7, no.1, pp. 34-47, Jan. 1998.
    • (1998) J. Multi-Criteria Decis. Anal. , vol.7 , Issue.1 , pp. 34-47
    • Jaszkiewicz, A.1    Czyzak, P.2
  • 19
    • 0033318858 scopus 로고    scopus 로고
    • Multiobjective evolutionary algorithms: A comparative case study and the strength Pareto approach
    • Nov.
    • E. Zitzler and L. Thiele, "Multiobjective evolutionary algorithms: A comparative case study and the strength Pareto approach," IEEE Trans. Evol. Comput., vol.3, no.4, pp. 257-271, Nov. 1999.
    • (1999) IEEE Trans. Evol. Comput. , vol.3 , Issue.4 , pp. 257-271
    • Zitzler, E.1    Thiele, L.2
  • 23
    • 0142134961 scopus 로고    scopus 로고
    • Efficient evaluation of multifactor dependent system performance using fractional factorial design
    • Sep.
    • T. Berling and P. Runeson, "Efficient evaluation of multifactor dependent system performance using fractional factorial design," IEEE Trans. Softw. Eng., vol.29, no.9, pp. 769-781, Sep. 2003.
    • (2003) IEEE Trans. Softw. Eng. , vol.29 , Issue.9 , pp. 769-781
    • Berling, T.1    Runeson, P.2
  • 26
    • 42549162260 scopus 로고    scopus 로고
    • Power/performance/thermal design-space exploration for multicore architectures
    • May
    • M. Monchiero, R. Canal, and A. Gonzalez, "Power/performance/thermal design-space exploration for multicore architectures," IEEE Trans. Parallel Distrib. Syst., vol.19, no.5, pp. 666-681, May 2008.
    • (2008) IEEE Trans. Parallel Distrib. Syst. , vol.19 , Issue.5 , pp. 666-681
    • Monchiero, M.1    Canal, R.2    Gonzalez, A.3
  • 27
    • 0030149507 scopus 로고    scopus 로고
    • CACTI: An enhanced cache access and cycle time model
    • May
    • S. Wilton and N. Jouppi, "CACTI: An enhanced cache access and cycle time model," IEEE J. Solid-State Circuits, vol.31, no.5, pp. 677-688, May 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , Issue.5 , pp. 677-688
    • Wilton, S.1    Jouppi, N.2
  • 28
    • 0033719421 scopus 로고    scopus 로고
    • WATTCH: A framework for architectural-level power analysis and optimizations
    • D. Brooks, V. Tiwari, and M. Martonosi, "WATTCH: A framework for architectural-level power analysis and optimizations," in Proc. ISCA, 2000, pp. 83-94.
    • (2000) Proc. ISCA , pp. 83-94
    • Brooks, D.1    Tiwari, V.2    Martonosi, M.3
  • 29
    • 52649107085 scopus 로고    scopus 로고
    • Variation-aware application scheduling and power management for chip multiprocessors
    • R. Teodorescu and J. Torrellas, "Variation-aware application scheduling and power management for chip multiprocessors," in Proc. 35th ISCA, 2008, pp. 363-374.
    • (2008) Proc. 35th ISCA , pp. 363-374
    • Teodorescu, R.1    Torrellas, J.2
  • 30
    • 57749178620 scopus 로고    scopus 로고
    • System level analysis of fast, per-core DVFs using on-chip switching regulators
    • Feb.
    • W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks, "System level analysis of fast, per-core DVFs using on-chip switching regulators," in Proc. IEEE 14th Int. Symp. HPCA, Feb. 2008, pp. 123-134.
    • (2008) Proc. IEEE 14th Int. Symp. HPCA , pp. 123-134
    • Kim, W.1    Gupta, M.S.2    Wei, G.-Y.3    Brooks, D.4
  • 31
    • 52649148744 scopus 로고    scopus 로고
    • Self-optimizing memory controllers: A reinforcement learning approach
    • Jun.
    • E. Ipek, O. Mutlu, J. F. Martinez, and R. Caruana, "Self-optimizing memory controllers: A reinforcement learning approach," in Proc. 35th ISCA, Jun. 2008, pp. 39-50.
    • (2008) Proc. 35th ISCA , pp. 39-50
    • Ipek, E.1    Mutlu, O.2    Martinez, J.F.3    Caruana, R.4
  • 37
    • 84894591387 scopus 로고    scopus 로고
    • Standard Performance Evaluation Corporation. [Online]. Available
    • Standard Performance Evaluation Corporation, SPEC CPU2006. [Online]. Available: www.spec.org/cpu 2006
    • (2006) SPEC CPU


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.