-
1
-
-
85008540166
-
Platform tuning for embedded systems design
-
Vahid F., and Givargis T. Platform tuning for embedded systems design. IEEE Computer 34 3 (2001) 112-114
-
(2001)
IEEE Computer
, vol.34
, Issue.3
, pp. 112-114
-
-
Vahid, F.1
Givargis, T.2
-
5
-
-
0033299117
-
-
G. Hekstra, D.L. Hei, P. Bingley, F. Sijstermans, TriMedia CPU64 design space exploration, in: International Conference on Computer Design, Austin, TX, 1999, pp. 599-606.
-
-
-
-
6
-
-
34248515427
-
-
S.G. Abraham, B.R. Rau, R. Schreiber, Fast design space exploration through validity and quality filtering of subsystem designs, Tech. Rep. HPL-2000-98, HP Laboratories Palo Alto (July 2000).
-
-
-
-
7
-
-
3042656853
-
-
R. Szymanek, F. Catthoor, K. Kuchcinski, Time-energy design space exploration for multi-layer memory architectures, in: Design, Automation and Test in Europe, 2004, pp. 181-190.
-
-
-
-
8
-
-
34248504626
-
-
S. Neema, J. Sztipanovits, G. Karsai, Design-space construction and exploration in platform-based design, Tech. Rep. ISIS-02-301, Institute for Software Integrated Systems Vanderbilt University Nashville Tennessee 37235 (June 2002).
-
-
-
-
10
-
-
0242577987
-
Statistical simulation: adding efficiency to the computer designer's toolbox
-
Eeckhout L., Nussbaum S., Smith J.E., and Bosschere K.D. Statistical simulation: adding efficiency to the computer designer's toolbox. IEEE Micro 23 5 (2003) 26-38
-
(2003)
IEEE Micro
, vol.23
, Issue.5
, pp. 26-38
-
-
Eeckhout, L.1
Nussbaum, S.2
Smith, J.E.3
Bosschere, K.D.4
-
11
-
-
34047158789
-
-
S. Eyerman, L. Eechhout, K.D. Bosschere, Efficient design space exploration of high performance embedded out-of-order processors, in: DATE, 2006.
-
-
-
-
13
-
-
34248519218
-
-
C.J. Alpert, L.W. Hagen, A.B. Kahng, A hybrid multilevel/genetic approach for circuit partitioning, in: Fifth ACM/SIGDA Physical Design Workshop, 1996, pp. 100-105.
-
-
-
-
14
-
-
0025430950
-
A genetic approach to standard cell placement using metagenetic parameter optimization
-
Shahookar K., and Mazumder P. A genetic approach to standard cell placement using metagenetic parameter optimization. IEEE Transactions on Computer-Aided Design 9 (1990) 500-511
-
(1990)
IEEE Transactions on Computer-Aided Design
, vol.9
, pp. 500-511
-
-
Shahookar, K.1
Mazumder, P.2
-
15
-
-
0005470830
-
A genetic algorithm for channel routing in VLSI circuits
-
Lienig J., and Thulasiraman K. A genetic algorithm for channel routing in VLSI circuits. Evolutionary Computation 1 4 (1993) 293-311
-
(1993)
Evolutionary Computation
, vol.1
, Issue.4
, pp. 293-311
-
-
Lienig, J.1
Thulasiraman, K.2
-
16
-
-
0030655539
-
-
Y.-M. Jiang, K.-T. Cheng, A. Krstic, Estimation of maximum power and instantaneous current using a genetic algorithm, in: Proceedings of IEEE Custom Integrated Circuits Conference, 1997, pp. 135-138.
-
-
-
-
17
-
-
0027872976
-
-
V. Kommu, I. Pomenraz, GAFAP: Genetic algorithm for FPGA technology mapping, in: European Design Automation Conference, 1993, pp. 300-305.
-
-
-
-
18
-
-
0029354779
-
Recent developments in netlist partitioning: a survey
-
Alpert C.J., and Kahng A.B. Recent developments in netlist partitioning: a survey. VLSI Journal 19 1-2 (1995) 1-81
-
(1995)
VLSI Journal
, vol.19
, Issue.1-2
, pp. 1-81
-
-
Alpert, C.J.1
Kahng, A.B.2
-
19
-
-
0030263862
-
Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms
-
Saab D., Saab Y., and Abraham J. Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. IEEE Transactions on Computer-Aided Design 15 10 (1996) 1278-1285
-
(1996)
IEEE Transactions on Computer-Aided Design
, vol.15
, Issue.10
, pp. 1278-1285
-
-
Saab, D.1
Saab, Y.2
Abraham, J.3
-
20
-
-
0034835932
-
-
G. Ascia, V. Catania, M. Palesi, Parameterized system design based on genetic algorithms, in: 9th International Symposium on Hardware/Software Co-Design, Copenhagen, Denmark, 2001, pp. 177-182.
-
-
-
-
21
-
-
4444356709
-
A GA based design space exploration framework for parameterized system-on-a-chip platforms
-
Ascia G., Catania V., and Palesi M. A GA based design space exploration framework for parameterized system-on-a-chip platforms. IEEE Transactions on Evolutionary Computation 8 4 (2004) 329-346
-
(2004)
IEEE Transactions on Evolutionary Computation
, vol.8
, Issue.4
, pp. 329-346
-
-
Ascia, G.1
Catania, V.2
Palesi, M.3
-
22
-
-
0034821356
-
-
W. Fornaciari, D. Sciuto, C. Silvano, V. Zaccaria, A design framework to efficiently explore energy-delay tradeoffs, in: 9th International Symposium on Hardware/Software Co-Design, Copenhagen, Denmark, 2001, pp. 260-265.
-
-
-
-
23
-
-
34248517216
-
-
G. Ascia, V. Catania, M. Palesi, Tuning methodologies for parameterized systems design, in: K.A. Publisher (Ed.), System on Chip for Realtime Systems, 2002.
-
-
-
-
24
-
-
34248513522
-
-
E. Zitzler, M. Laumanns, L. Thiele, SPEA2: Improving the performance of the strength pareto evolutionary algorithm, in: EUROGEN 2001, Evolutionary Methods for Design, Optimization and Control with Applications to Industrial Problems, Athens, Greece, 2001, pp. 95-100.
-
-
-
-
25
-
-
0033318858
-
Multiobjective evolutionary algorithms: a comparative case study and the strength pareto approach
-
Zitzler E., and Thiele L. Multiobjective evolutionary algorithms: a comparative case study and the strength pareto approach. IEEE Transactions on Evolutionary Computation 4 3 (1999) 257-271
-
(1999)
IEEE Transactions on Evolutionary Computation
, vol.4
, Issue.3
, pp. 257-271
-
-
Zitzler, E.1
Thiele, L.2
-
27
-
-
0021892282
-
Fuzzy identification of systems and its application to modeling and control
-
Takagi T., and Sugeno M. Fuzzy identification of systems and its application to modeling and control. IEEE Transactions on System, Man and Cybernetics 15 (1985) 116-132
-
(1985)
IEEE Transactions on System, Man and Cybernetics
, vol.15
, pp. 116-132
-
-
Takagi, T.1
Sugeno, M.2
-
28
-
-
0020632876
-
-
J.A. Fisher, Very long instruction word architectures and the ELI512, in: Tenth Annual International Symposium on Computer Architecture, 1983, pp. 140-150.
-
-
-
-
29
-
-
34248553582
-
-
An infrastructure for research in instruction-level parallelism. .
-
-
-
-
30
-
-
34248564588
-
-
G. Ascia, V. Catania, M. Palesi, D. Patti, EPIC-Explorer: a parameterized VLIW-based platform framework for design space exploration, in: First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Newport Beach, California, USA, 2003, pp. 65-72.
-
-
-
-
31
-
-
34248506568
-
-
D. Patti, M. Palesi, EPIC-Explorer. (July 2003).
-
-
-
-
32
-
-
27644483709
-
Approximation capabilities of hierarchical fuzzy systems
-
Zeng X.-J., and Keane J.A. Approximation capabilities of hierarchical fuzzy systems. IEEE Transactions on Fuzzy Systems 13 5 (2005) 659-672
-
(2005)
IEEE Transactions on Fuzzy Systems
, vol.13
, Issue.5
, pp. 659-672
-
-
Zeng, X.-J.1
Keane, J.A.2
-
33
-
-
0037936618
-
Performance assessment of multiobjective optimizers: an analysis and review
-
Zitzler E., Thiele L., Laumanns M., Fonseca C.M., and da Fonseca V.G. Performance assessment of multiobjective optimizers: an analysis and review. IEEE Transactions on Evolutionary Computation 7 2 (2003) 117-132
-
(2003)
IEEE Transactions on Evolutionary Computation
, vol.7
, Issue.2
, pp. 117-132
-
-
Zitzler, E.1
Thiele, L.2
Laumanns, M.3
Fonseca, C.M.4
da Fonseca, V.G.5
-
34
-
-
34248559609
-
-
J.D. Knowles, L. Thiele, E. Zitzler, A tutorial on the performance assessment of stochastive multiobjective optimizers, Tech. Rep. TIK-Report No. 214, Computer Engineering and Networks Laboratory, ETH Zurich, Swiss (February 2006). .
-
-
-
|