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Volumn , Issue , 2007, Pages 327-338

Using predictive modeling for cross-program design space exploration in multicore systems

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION RANGE; COMPILATION TECHNIQUES; DELAY METRIC; DESIGN SPACES; EXECUTION TIME; FABRICATION TECHNOLOGIES; IN-CHIP; INTERNATIONAL CONFERENCES; MACHINE-LEARNING; MULTI CORE SYSTEMS; NEW APPLICATIONS; ORDERS-OF-MAGNITUDE; PARALLEL APPLICATIONS; PARALLEL ARCHITECTURES; PERFORMANCE METRICS; PREDICTION ERRORS; PREDICTIVE MODELING; PROGRAM DESIGN; THREAD-LEVEL SPECULATION;

EID: 47849123249     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2007.4336223     Document Type: Conference Paper
Times cited : (64)

References (25)
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    • Recovery Requirements of Branch Prediction Storage Structures in the Presence of Mispredicted-Path Execution
    • S. Jourdan, J. Stark, T. H. Hsing, and Y. N. Patt. "Recovery Requirements of Branch Prediction Storage Structures in the Presence of Mispredicted-Path Execution." Intl. Journal of Parallel Programming, 25(5), pages 363-383, 1997.
    • (1997) Intl. Journal of Parallel Programming , vol.25 , Issue.5 , pp. 363-383
    • Jourdan, S.1    Stark, J.2    Hsing, T.H.3    Patt, Y.N.4
  • 14
    • 0001025418 scopus 로고
    • Bayesian Interpolation
    • D. J. C. MacKay. "Bayesian Interpolation." Neural Computation, 4(3), pages 415-447, 1992.
    • (1992) Neural Computation , vol.4 , Issue.3 , pp. 415-447
    • MacKay, D.J.C.1
  • 15
    • 0003343363 scopus 로고
    • Combining Branch Predictors
    • S. McFarling. "Combining Branch Predictors." WRL Technical Note, TN-36, 1993.
    • (1993) WRL Technical Note , vol.TN-36
    • McFarling, S.1
  • 16
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    • A Machine Learning Approach to Automatic Production of Compiler Heuristics
    • Intl. Conf. on Artificial Intelligence: Methodology, Systems, Applications
    • A. Monsifrot, F. Bodin, and R. Quiniou. "A Machine Learning Approach to Automatic Production of Compiler Heuristics." Intl. Conf. on Artificial Intelligence: Methodology, Systems, Applications, LNCS 2443, pages 41-50, 2002.
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    • Monsifrot, A.1    Bodin, F.2    Quiniou, R.3
  • 18
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    • Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation
    • June
    • J. Renau, J. Tuck, W. Liu, L. Ceze, K. Strauss, and J. Torrellas. "Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation." Intl. Conf. on Supercomputing, pages 179-188, June 2005.
    • (2005) Intl. Conf. on Supercomputing , pp. 179-188
    • Renau, J.1    Tuck, J.2    Liu, W.3    Ceze, L.4    Strauss, K.5    Torrellas, J.6
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    • CACTI 3.0: An Integrated Cache Timing, Power, and Area Model
    • 2001/2
    • P. Shivakumar, and N. P. Jouppi. CACTI 3.0: An Integrated Cache Timing, Power, and Area Model. WRL Research Report, 2001/2.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.