Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation

Proceedings of 2011 SC - International Conference for High Performance Computing, Networking, Storage and Analysis

Volumn , Issue , 2011, Pages

  Carlson, Trevor E ^a,b   Heirman, Wim ^a,b   Eeckhout, Lieven ^a  

^a GHENT UNIVERSITY   (Belgium)

^b Intel Corporation Belgium   (Belgium)

Author keywords

Interval model; Interval simulation; Multi core processor; Performance modeling

Indexed keywords

ANALYTICAL MODEL; AVERAGE ABSOLUTE ERROR; CYCLE-ACCURATE SIMULATION; DESIGN SPACES; ENTIRE SYSTEM; HARDWARE DESIGN; HIGH-PERFORMANCE COMPUTING; INTERVAL MODELS; INTERVAL SIMULATION; LEVEL OF ABSTRACTION; MULTI CORE; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; MULTITHREADED; ON-CHIP CACHE; PARALLEL SIMULATIONS; PERFORMANCE MODELING; PROCESSOR ARCHITECTURES; SIMULATION SPEED; SIMULATION TIME; TRADE OFF;

CACHE MEMORY; CIRCUIT SIMULATION; COMPUTER SOFTWARE SELECTION AND EVALUATION; MATHEMATICAL MODELS; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; OCCUPATIONAL RISKS; PARALLEL PROCESSING SYSTEMS; PLASMA WAVES;

COMPUTER SIMULATION;

EID: 83155173614     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2063384.2063454     Document Type: Conference Paper

References (32)

1. A. Alameldeen and D. Wood. Variability in architectural simulations of multi-threaded workloads. In Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA), pages 7-18, Feb. 2003.
2. K. C. Barr, H. Pan, M. Zhang, and K. Asanovic. Accelerating multiprocessor simulation with a memory timestamp record. In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 66-77, Mar. 2005. (Pubitemid 43804304)
3. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), pages 72-81, Oct. 2008.
4. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The M5 simulator: Modeling networked systems. IEEE Micro, 26:52-60, 2006. (Pubitemid 46504889)
5. J. Chen, L. K. Dabbiru, D. Wong, M. Annavaram, and M. Dubois. Adaptive and speculative slack simulations of CMPs on CMPs. In Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 523-534. IEEE Computer Society, 2010.
6. D. Chiou, D. Sunwoo, J. Kim, N. A. Patil, W. Reinhart, D. E. Johnson, J. Keefe, and H. Angepat. FPGA-accelerated simulation technologies (FAST): Fast, full-system, cycle-accurate simulators. In Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 249-261, Dec. 2007.
7. T. M. Conte, M. A. Hirsch, and K. N. Menezes. Reducing state loss for effective trace sampling of superscalar processors. In Proceedings of the International Conference on Computer Design (ICCD), pages 468-477, Oct. 1996.
8. Y. Cui, W. Wu, Y. Wang, X. Guo, Y. Chen, and Y. Shi. A discrete event simulation model for understanding kernel lock thrashing on multi-core architectures. In Proceedings of the 16th International Conference on Parallel and Distributed Systems (ICPADS), pages 1-8, Dec. 2010.
9. M. Ekman and P. Stenström. Enhancing multiprocessor architecture simulation speed using matched-pair comparison. In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 89-99, Mar. 2005. (Pubitemid 43804306)
10. S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A mechanistic performance model for superscalar out-of-order processors. ACM Transactions on Computer Systems (TOCS), 27(2):42-53, May 2009.
11. A. Fog. Instruction tables. http//www.agner.org/optimize/instruction- tables.pdf, April 2011.
12. H. Franke, R. Russell, and M. Kirkwood. Fuss, futexes and furwocks: Fast userlevel locking in Linux. In Proceedings of the 2002 Ottawa Linux Summit, pages 479-495, 2002.
13. R. M. Fujimoto. Parallel discrete event simulation. Communications of the ACM, 33(10):30-53, Oct. 1990.
14. D. Genbrugge, S. Eyerman, and L. Eeckhout. Interval simulation: Raising the level of abstraction in architectural simulation. In Proceedings of the 16th International Symposium on High Performance Computer Architecture (HPCA), pages 307-318, Feb. 2010.
15. L. Hammond, V. Wong, M. Chen, B. D. Carlstrom, J. D. D. an B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional memory coherence and consistency. In Proceedings of the International Symposium on Computer Architecture (ISCA), pages 102-113, June 2004.
16. A. Jaleel, R. S. Cohn, C.-K. Luk, and B. Jacob. CMP$im: A Pin-based on-the-fly multi-core cache simulator. In Proceedings of the Fourth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS), co-located with ISCA 2008, pages 28-36, June 2008.
17. A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely, Jr., and J. Emer. Adaptive insertion policies for managing shared caches. In Proceedings of the 17th international conference on Parallel architectures and compilation techniques (PACT), pages 208-219, 2008.
18. B. Lee, J. Collins, H. Wang, and D. Brooks. CPR: Composable performance regression for scalable multiprocessor models. In Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 270-281, Nov. 2008.
19. C.-K. Luk, R. Cohn, R. Muth, H. Patil, A. Klauser, G. Lowney, S. Wallace, V. J. Reddi, and K. Hazelwood. Pin: building customized program analysis tools with dynamic instrumentation. In Proceedings of the 2005 ACM SIGPLAN conference on Programming Language Design and Implementation (PLDI), pages 190-200. ACM, June 2005.
20. M. K. Martin, D. J. Sorin, B. M. Beckmann, M. R. Marty, M. Xu, A. R. Alameldeen, K. E. Moore, M. D. Hill, and D. A. Wood. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. ACM SIGARCH Computer Architecture News, 33(4):92-99, Nov. 2005.
21. A. M. G. Maynard, C. M. Donnelly, and B. R. Olszewski. Contrasting characteristics and cache performance of technical and multi-user commercial workloads. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 145-156, Oct. 1994.
22. J. E. Miller, H. Kasture, G. Kurian, C. Gruenwald III, N. Beckmann, C. Celio, J. Eastep, and A. Agarwal. Graphite: A distributed parallel simulator for multicores. In Proceedings of the 16th International Symposium on High Performance Computer Architecture (HPCA), pages 1-12, Jan. 2010.
23. K. E. Moore, J. Bobba, M. J. Moravan, M. D. Hill, and D. A. Wood. LogTM: Log-based transactional memory. In Proceedings of the 13th International Symposium on High Performance ComputerArchitecture (HPCA), pages 254-265, Feb. 2006.
24. M. Pellauer, M. Adler, M. Kinsy, A. Parashar, and J. Emer. HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. In Proceedings of the 17th International Symposium on High Performance Computer Architecture (HPCA), pages 406-417, Feb. 2011.
25. S. K. Reinhardt, M. D. Hill, J. R. Larus, A. R. Lebeck, J. C. Lewis, and D. A. Wood. The Wisconsin Wind Tunnel: Virtual prototyping of parallel computers. In Proceedings of the ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, pages 48-60, May 1993.
26. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 45-57, Oct. 2002. (Pubitemid 44892222)
27. D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon, and D. A. Wood. Analytic evaluation of shared-memory systems with ILP processors. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA), pages 380-391, June 1998.
28. V. Uzelac and A. Milenkovic. Experiment ows and microbenchmarks for reverse engineering of branch predictor structures. In 2009 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 207-217, 2009.
29. J. Wawrzynek, D. Patterson, M. Oskin, S.-L. Lu, C. Kozyrakis, J. C. Hoe, D. Chiou, and K. Asanovic. RAMP: Research accelerator for multiple processors. IEEE Micro, 27(2):46-57, Mar. 2007. (Pubitemid 47322500)
30. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 programs: Characterization and methodological considerations. In Proceedings of the 22nd International Symposium on Computer Architecture (ISCA), pages 24-36, June 1995.
31. R. E. Wunderlich, T. F. Wenisch, B. Falsafi, and J. C. Hoe. SMARTS: Accelerating microarchitecture simulation via rigorous statistical sampling. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pages 84-95, June 2003.
32. M. Yourst. PTLsim: A cycle accurate full system x86-64 microarchitectural simulator. In Proceedings of the 2007 IEEE International Symmposium on Performance Analysis of Systems and Software (ISPASS), pages 23-34. Apr. 2007. (Pubitemid 350237483)