Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation

Proceedings of the 12th Annual Genetic and Evolutionary Computation Conference, GECCO '10

Volumn , Issue , 2010, Pages 1267-1274

  Ceriani, Marco ^a   Ferrandi, Fabrizio ^a   Lanzi, Pier Luca ^a   Sciuto, Donatella ^a   Turneo, Antonino ^b  

^a POLITECNICO DI MILANO   (Italy)

^b PACIFIC NORTHWEST NATIONAL LABORATORY   (United States)

Author keywords

Algorithms; Design

Indexed keywords

COMMUNICATION INFRASTRUCTURE; EVOLUTIONARY COMPUTATIONS; HARDWARE ACCELERATORS; MEMORY BUFFERS; MULTI OBJECTIVE; MULTI PROCESSOR SYSTEMS; MULTI RATE; MULTI-OBJECTIVE GENETIC ALGORITHM; MULTIPROCESSOR SYSTEMS ON CHIPS; OPTIMAL ARCHITECTURE; PROCESSING ELEMENTS; REAL-TIME APPLICATION; SOFT DEADLINES;

CALCULATIONS; COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; FAULT TOLERANCE; MULTIOBJECTIVE OPTIMIZATION; MULTIPROCESSING SYSTEMS; QUALITY ASSURANCE; REAL TIME SYSTEMS; SIMULATED ANNEALING; TABU SEARCH;

EVOLUTIONARY ALGORITHMS;

EID: 77955860548     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1830483.1830710     Document Type: Conference Paper

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