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Volumn , Issue , 2008, Pages 606-609

Input vector control for post-silicon leakage current minimization in the presence of manufacturing variability

Author keywords

Input vector control; Low power; Manufacturing variability

Indexed keywords

INPUT VECTOR CONTROL; INPUT VECTORS; LOW POWER; MANUFACTURING VARIABILITY;

EID: 51549088218     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2008.4555889     Document Type: Conference Paper
Times cited : (35)

References (15)
  • 1
    • 1642414282 scopus 로고    scopus 로고
    • Leakage current reduction in CMOS VLSI circuits by input vector control
    • A. Abdollahi, F. Fallah, and M. Pedram. Leakage current reduction in CMOS VLSI circuits by input vector control. IEEE Trans. VLSI, 12(2):140-154, 2004.
    • (2004) IEEE Trans. VLSI , vol.12 , Issue.2 , pp. 140-154
    • Abdollahi, A.1    Fallah, F.2    Pedram, M.3
  • 2
    • 85077688405 scopus 로고    scopus 로고
    • Active hardware metering for intellectual properly protection and security
    • Y. Alkabani and F. Koushanfar. Active hardware metering for intellectual properly protection and security. In USEN DC Security, pages 291-306. 2007.
    • (2007) USEN DC Security , pp. 291-306
    • Alkabani, Y.1    Koushanfar, F.2
  • 3
    • 51549103580 scopus 로고    scopus 로고
    • Input vector control for post-silicon leakage current minimization under manufacturing variations
    • Technical report. Rice University, Electrical and Computer Engineering Department
    • Y. Alkabani, T. Massey, F. Koushanfar, and M. Potkonjak. Input vector control for post-silicon leakage current minimization under manufacturing variations. Technical report. Rice University, Electrical and Computer Engineering Department, 2008.
    • (2008)
    • Alkabani, Y.1    Massey, T.2    Koushanfar, F.3    Potkonjak, M.4
  • 6
    • 27944470947 scopus 로고    scopus 로고
    • Full-chip analysis of leakage power under process variations, including spatial correlations
    • H. Chang and S. Sapatnekar. Full-chip analysis of leakage power under process variations, including spatial correlations. In DAC, pages 523-528, 2005.
    • (2005) DAC , pp. 523-528
    • Chang, H.1    Sapatnekar, S.2
  • 7
    • 34547206809 scopus 로고    scopus 로고
    • A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction
    • L. Cheng, L. Deng, D. Chen, and M. Wong. A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction. In DAC, pages 117-120,2006.
    • (2006) DAC , pp. 117-120
    • Cheng, L.1    Deng, L.2    Chen, D.3    Wong, M.4
  • 8
    • 84886673851 scopus 로고    scopus 로고
    • Modeling within-die spatial correlation effects for process-design co-optimization
    • P. Friedbere, Y. Cao, J. Cain, R. Wang. J. Rabaey. and C. Spanos. Modeling within-die spatial correlation effects for process-design co-optimization. In ISQED, pages 516-521. 2005.
    • (2005) ISQED , pp. 516-521
    • Friedbere, P.1    Cao, Y.2    Cain, J.3    Wang, R.4    Rabaey, J.5    Spanos, C.6
  • 10
    • 34547252533 scopus 로고    scopus 로고
    • CAD-based security, cryptography, and digital lights management
    • F. Koushanfar and M. Potkonjak. CAD-based security, cryptography, and digital lights management. In DAC, pages 268-269, 2007.
    • (2007) DAC , pp. 268-269
    • Koushanfar, F.1    Potkonjak, M.2
  • 11
    • 15244338765 scopus 로고    scopus 로고
    • Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile
    • S. Mukhopadhyay, A. Raychowdhury, and K. Roy. Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. IEEE Trans. on CAD, 24(3):363-381, 2005.
    • (2005) IEEE Trans. on CAD , vol.24 , Issue.3 , pp. 363-381
    • Mukhopadhyay, S.1    Raychowdhury, A.2    Roy, K.3
  • 12
    • 0036443068 scopus 로고    scopus 로고
    • Finding a small set of longest testable paths that cover every gate
    • M. Sharma and J. Patel. Finding a small set of longest testable paths that cover every gate. In ITC, pages 974-982, 2002.
    • (2002) ITC , pp. 974-982
    • Sharma, M.1    Patel, J.2
  • 14
    • 0028722375 scopus 로고    scopus 로고
    • V. Tiwari, S. Malik, and A. Wolfe. Power analysis of embedded software: a first step towards softwarepower minimization. 2(4):437-455, 1994.
    • V. Tiwari, S. Malik, and A. Wolfe. Power analysis of embedded software: a first step towards softwarepower minimization. 2(4):437-455, 1994.
  • 15
    • 33645009272 scopus 로고    scopus 로고
    • A combined gate replacement and input vector control approach for leakage current reduction
    • L. Yuan and G. Qu. A combined gate replacement and input vector control approach for leakage current reduction. IEEE Trans. on VLSI, 14(2):173-182, 2006.
    • (2006) IEEE Trans. on VLSI , vol.14 , Issue.2 , pp. 173-182
    • Yuan, L.1    Qu, G.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.