Design of massively parallel hardware multi-processors for highly-demanding embedded applications

Microprocessors and Microsystems

Volumn 37, Issue 8 PARTD, 2013, Pages 1155-1172

  Jóźwiak, Lech ^a   Jan, Yahya ^a,b  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b not available   (Netherlands)

Author keywords

4G 5G communication systems; Design space exploration; EDA tools; Highly demanding applications; LDPC decoding; Massively parallel MPSoCs; Micro and macro architectures; Scalable memory and communication architectures

Indexed keywords

COMMERCE; DECODING; ENERGY UTILIZATION; HARDWARE; MEMORY ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; SYSTEM-ON-CHIP;

COMMUNICATION ARCHITECTURES; DESIGN SPACE EXPLORATION; EDA TOOLS; LDPC DECODING; MASSIVELY PARALLELS; MICRO AND MACRO;

INTEGRATED CIRCUIT DESIGN;

EID: 84888290388     PISSN: 01419331     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.micpro.2013.09.005     Document Type: Article

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