Flexible LDPC decoder architecture for high-throughput applications

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 45-48

  Kim, Sangmin ^a   Sobelman, Gerald E ^a   Lee, Hanho ^b  

^a University of Minnesota   (United States)

^b Inha University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK SIZES; CHECK NODES; CODE RATES; HIGH THROUGHPUTS; IEEE 802.11N; IEEE 802.15.3C; IEEE 802.16E; LAYERED DECODING; LDPC CODES; LDPC DECODERS; MEMORY BANKS; PARALLEL SCHEDULING; PROPOSED ARCHITECTURES; SYSTEM FLEXIBILITIES; WIRELESS APPLICATIONS;

SCHEDULING; STANDARDS; THROUGHPUT;

DECODING;

EID: 62949152337     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4745956     Document Type: Conference Paper

References (11)

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