Quality-driven methodology for demanding accelerator design

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 380-389

  Jóźwiak, Lech ^a   Jan, Yahya ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

Architecture design; Combined macro and micro architecture design; Design space exploration; Hardware accelerators

Indexed keywords

ACCELERATOR DESIGN; ARCHITECTURE DESIGN; ARCHITECTURE DESIGNS; COMMUNICATION SYSTEM STANDARD; HARDWARE ACCELERATORS; LDPC CODES; MICRO-ARCHITECTURE DESIGN;

ACCELERATION; CODING ERRORS; COMMUNICATION SYSTEMS; SPACE RESEARCH;

DESIGN;

EID: 77952663524     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450546     Document Type: Conference Paper

References (22)

1. L. Jóźwiak, A. Douglas: Hardware Synthesis for Reconfigurable Pipelined Accelerators, Proc. Of ITNG'2008 - IEEE International Conference on Information Technology: Mew Generations, Las Vegas, NV, USA, April 7-9, 2008, IEEE Computer Society Press, Los Alamitos, CA, USA, pp. 1123-1130.
2. th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, Samos, Greece, July 20-23, 2009, LNCS 5657, Springer-Verlag, Berlin Heidelberg, Germany, pp. 24-35.
3. L. Jóźwiak: Quality-driven Design in the System-on-a-Chip Era: Why and How? Journal of Systems Architecture, Elsevier Science, Amsterdam, The Netherlands, 2001, Vol. 47/3-4, pp. 201-224.
4. L. Jóźwiak, N. Nedjah and M. Figueroa: Modern Development Methods and Tools for Embedded Reconfigurable Systems - a Survey, Integration - The VLSI Journal, Elsevier Science, Volume 43, No 1, January 2010, pp. 1-33.
5. R. Schreiber at al: High-level synthesis of nonprogrammable hardware accelerators, Proc. of ASAP'2000, pp. 113-124.
6. K. Kuchcinski, C. Wolinski: Global approach to assignment and scheduling of complex behaviours based on HCDG and constraint programming, Journal of Systems Architecture, Vol. 49, 2003, pp. 489-503.
7. S. Gupta, N. Dutt, R. Gupta, A. Nicolau, SPARK: A high-level synthesis framework for applying parallelizing compiler transformations, Proc. Int. Conf. on VLSI Design, 2003, pp. 461-466.
8. Z. Guo, B. Buyukkurt, W. Najjar, and K. Vissers: Optimized generation of data-path from C codes for FPGAs, Proc. DATE'05, 2005, pp. 112-117.
9. M. Puschel at al: SPIRAL: Code generation for DSP transforms, Proceedings of the IEEE, Vol. 93, No. 2, 2005, pp. 232-275.
10. S. Sun, W. Wirthlin, M. J. Neuendorffer: FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing, IEEE Trans. on CAD, Vol. 26, No.2, 2007, pp. 254-265.
11. S,P Mohanty, N. Ranganathan, E. Kougianos, P. Patra, P.: Low-Power High-Level Synthesis for Nanoscale CMOS Circuits, Springer, 2008, pp. 1-298.
12. Synfora PICO platform for accelerator synthesis from C, http://www.synfora.com/.
13. R. Tanner: A recursive approach to low complexity codes, IEEE Trans. on Inf. Theory, 27(5), 1981, pp. 533-547.
14. D.J.C. MacKay: Good error-correcting codes based on very sparse matrices, IEEE Trans. on Inf. Theory, 45(2), 1999, pp. 399-431.
15. G. Malema and M. Liebelt: Interconnection Network for Structured Low-Density Parity-Check Decoders, Proc. 2005 Asia-Pacific Conf. on Communications, 2005, pp. 537-540.
16. M.M. Mansour and N.R. Shanbhag: High-throughput LDPC decoders. IEEE Trans. on VLSI System, 11(6), 2003, pp. 976-996.
17. E. Yeo, P. Pakzad, B. Nikolic and V. Anantharam: VLSI Architectures for Iterative Decoders in Magnetic Recording Channels, IEEE Trans. on Magnetics, 37, 2001, pp. 748-755.
18. A. Darabiha, A.C. Carusone and F.R. Kschischang: Multi-Gbit/sec low density parity check decoders with reduced interconnect complexity, Proc. ISCAS'2005, 2005, pp. 5194-5197.
19. K. Gunnam, G. Choi, W. Wang and M. Yeary: Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard, Proc. ISCAS'2007, 2007, pp. 1645-1648.
20. K. Sangmin, G.E. Sobelman and H. Lee: Flexible LDPC decoder architecture for high-throughput applications, Proc. APCCAS'2008, 2008, pp. 45-48.
21. L. Zhang, L. Gui, Y. Xu and W. Zhang: Configurable Multi-Rate Decoder Architecture for QC-LDPC Codes Based Broadband Broadcasting System, IEEE Trans. on Broadcasting, 54(2), 2008, pp. 226-235.
22. Z. Cui, Z. Wang and Y. Liu: High-Throughput Layered LDPC Decoding Architecture, IEEE Trans. on VLSI Systems, 17(4), 2009, pp. 582-587.