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Volumn , Issue , 2007, Pages 1645-1648

Multi-rate layered decoder architecture for block LDPC codes of the IEEE 802.11n wireless standard

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MESSAGE PASSING; SCHEDULING; SIGNAL ENCODING; STANDARDS;

EID: 34548840321     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378835     Document Type: Conference Paper
Times cited : (49)

References (16)
  • 1
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    • D. MacKay and R. Neal, "Near shannon limit performance of low density parity check codes", Electronics Letters, volume 32, pp. 1645-1646, Aug 1996.
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    • MacKay, D.1    Neal, R.2
  • 3
    • 33644640388 scopus 로고    scopus 로고
    • A 640-Mb/s 2048-bit programmable LDPC decoder chip
    • March
    • M. Mansour and N. Shanbhag, "A 640-Mb/s 2048-bit programmable LDPC decoder chip," IEEE J. of Solid-State Circuits, vol. 41, no.3, pp. 684-698, March 2006.
    • (2006) IEEE J. of Solid-State Circuits , vol.41 , Issue.3 , pp. 684-698
    • Mansour, M.1    Shanbhag, N.2
  • 4
    • 4444270737 scopus 로고    scopus 로고
    • Memory-efficient sum-product decoding of LDPC codes
    • Aug
    • H. Sankar and K. Narayanan, "Memory-efficient sum-product decoding of LDPC codes," IEEE Trans. on Communications, vol.52, pp. 1225-1230, Aug. 2004.
    • (2004) IEEE Trans. on Communications , vol.52 , pp. 1225-1230
    • Sankar, H.1    Narayanan, K.2
  • 5
    • 17044383428 scopus 로고    scopus 로고
    • A reduced complexity decoder architecture via layered decoding of LDPC codes
    • Oct
    • D. Hocevar, "A reduced complexity decoder architecture via layered decoding of LDPC codes," Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on, pp. 107-112, Oct. 2004.
    • (2004) Signal Processing Systems, 2004. SIPS 2004. IEEE Workshop on , pp. 107-112
    • Hocevar, D.1
  • 6
    • 0036504121 scopus 로고    scopus 로고
    • A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder
    • Mar
    • A. Blanksby, C. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder", IEEE J. Solid-State Circuits, Vol.37, Iss.3, pp. 404-412, Mar 2002.
    • (2002) IEEE J. Solid-State Circuits , vol.37 , Issue.ISS.3 , pp. 404-412
    • Blanksby, A.1    Howland, C.2
  • 10
    • 47049086361 scopus 로고    scopus 로고
    • K. Gunnam, G. Choi, W. Wang, E. Kim and M. B. Yeary, Decoding of Quasi-cyclic LDPC Codes using an On-The-Fly Computation, Accepted for 40th Asilomar Conf. on Signals, Systems and Computers, October 2006.
    • K. Gunnam, G. Choi, W. Wang, E. Kim and M. B. Yeary, "Decoding of Quasi-cyclic LDPC Codes using an On-The-Fly Computation," Accepted for 40th Asilomar Conf. on Signals, Systems and Computers, October 2006.
  • 11
    • 18144396564 scopus 로고    scopus 로고
    • Block-LDPC: A practical LDPC coding system design approach
    • April
    • H. Zhong, T. Zhang, "Block-LDPC: a practical LDPC coding system design approach," IEEE Trans. on Circuits and Systems I, vol.52, no.4, pp. 766-775, April 2005.
    • (2005) IEEE Trans. on Circuits and Systems I , vol.52 , Issue.4 , pp. 766-775
    • Zhong, H.1    Zhang, T.2
  • 12
    • 34548862485 scopus 로고    scopus 로고
    • IEEE 802.16e WiMax Standard, IEEE P802.16e-2005, October 2005.
    • IEEE 802.16e WiMax Standard, IEEE P802.16e-2005, October 2005.
  • 14
    • 34548111053 scopus 로고    scopus 로고
    • Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation
    • October, Online, Available
    • K. Gunnam, "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation," PhD Dissertation, Texas A&M University, October 2006.[Online]. Available: http://dropzone.tamu.edu/techpubs.
    • (2006) PhD Dissertation, Texas A&M University
    • Gunnam, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.