A 135Mb/s DVB-S2 compliant codec based on 64800b LDPC and BCH codes

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Urard, P ^a   Yeo, E ^a   Paumier, L ^a   Georgelin, P ^a   Michel, T ^a   Lebars, V ^a   Lantreibecq, E ^a   Gupta, B ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 27944437120     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Draft ETSI EN 302 307 V1.1.1, 2004-06.
2. R. Bose and D. Ray-Chaudhuri, "On a Class of Error Correcting Binary Group Codes," Inform. Contr., vol. 3, pp. 68-69, 1960.
3. R. Gallager, "Low Density Parity Check Codes," IRE T. Inform. Theory, vol. IT-8, pp. 21, Jan. 28, 1962.
4. A. Blanksby and C. Rowland, "A 690-mW 1-Gbit/s 1024-bit Rate-1/2 Low Density Parity Check Code Decoder," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 404-412, Mar., 2002.
5. E. Yeo et al., "High Throughput Low-Density Parity-Check Architectures," Proc. IEEE Globecom 2001, pp. 3019-3024, San Antonio, TX, Nov., 25-29, 2001.
6. E. Jamro, "The Design of a VHDL Based Synthesis Tool for BCH Codecs", The University of Huddersfield, Sep., 1997.
7. P. Urard et al., "A Generic 350Mb/s Turbo-Codec Based on a 16-states SISO Decoder," ISSCC Dig. Tech. Papers, pp. 424-425, Feb., 2004.
8. P. Georgelin, "Formal Verification of Synchronous Digital Systems, Based on Symbolic Simulation," PhD Thesis, Université Joseph Fourier, France, 18 Oct., 2001.
9. E. Yeo, "High Throughput VLSI Architectures for Iterative Decoders," University of California at Berkeley, p. 88, 2003.