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Volumn , Issue , 2011, Pages 33-36

LegUp: High-level synthesis for FPGA-based processor/accelerator systems

Author keywords

[No Author keywords available]

Indexed keywords

C PROGRAMS; CUSTOM HARDWARES; HARDWARE DESIGN; HARDWARE SOLUTIONS; HIGH LEVEL SYNTHESIS; HYBRID ARCHITECTURES; OPEN SOURCES; SOFT PROCESSORS; SOFTWARE TECHNIQUES; STANDARD BUS;

EID: 79952981487     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1950413.1950423     Document Type: Conference Paper
Times cited : (471)

References (13)
  • 3
    • 84862931159 scopus 로고    scopus 로고
    • FPGA-based hardware acceleration of lithographic aerial image simulation
    • J. Cong and Y. Zou. FPGA-based hardware acceleration of lithographic aerial image simulation. ACM Trans. Reconfigurable Technol. Syst., 2(3):1-29, 2009.
    • (2009) ACM Trans. Reconfigurable Technol. Syst. , vol.2 , Issue.3 , pp. 1-29
    • Cong, J.1    Zou, Y.2
  • 6
    • 84862660545 scopus 로고    scopus 로고
    • Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis
    • Y. Hara, H. Tomiyama, S. Honda, and H. Takada. Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis. Journal of Information Processing, 17:242-254, 2009.
    • (2009) Journal of Information Processing , vol.17 , pp. 242-254
    • Hara, Y.1    Tomiyama, H.2    Honda, S.3    Takada, H.4
  • 8
    • 0025535964 scopus 로고
    • Data path allocation based on bipartite weighted matching
    • C.Y. Huang, Y.S. Che, Y.L. Lin, and Y.C. Hsu. Data path allocation based on bipartite weighted matching. In Design Automation Conference, volume 27, pages 499-504, 1990.
    • (1990) Design Automation Conference , vol.27 , pp. 499-504
    • Huang, C.Y.1    Che, Y.S.2    Lin, Y.L.3    Hsu, Y.C.4
  • 11
    • 79952935704 scopus 로고    scopus 로고
    • Univ. of Cambridge, http://www.cl.cam.ac.uk/teaching/0910/ECAD+Arch/mips. htmlThe Tiger "MIPS" processor., 2010.
    • (2010) The Tiger "MIPS" Processor.
  • 12
    • 48249084289 scopus 로고    scopus 로고
    • Warp processing: Dynamic translation of binaries to FPGA circuits
    • F. Vahid, G. Stitt, and Lysecky, R. Warp processing: Dynamic translation of binaries to FPGA circuits. IEEE Computer, 41(7):40-46, 2008.
    • (2008) IEEE Computer , vol.41 , Issue.7 , pp. 40-46
    • Lysecky, R.1    Vahid, F.2    Stitt, G.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.