Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2008, Pages 1137-1142

  Studer, C ^a   Preyss, N ^b   Roth, C ^b   Burg, A ^a  

^a ETH ZURICH   (Switzerland)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; CONFIGURABLE; CORE AREA; DECODER ARCHITECTURE; HARDWARE ARCHITECTURE; HIGH-THROUGHPUT; IEEE 802.11N; LOW DENSITY PARITY CHECK; QC LDPC CODES; QUASI-CYCLIC LDPC CODES; QUASICYCLIC CODES; RE-CONFIGURABLE; VLSI IMPLEMENTATION;

CMOS INTEGRATED CIRCUITS; CODING ERRORS; COMMUNICATION CHANNELS (INFORMATION THEORY); QUANTUM THEORY; STANDARDS;

DECODING;

EID: 70349659697     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2008.5074592     Document Type: Conference Paper

References (17)

1. R. G. Gallager, "Low density parity check codes," Trans. of the IRE Professional Group on Inf. Theory, vol. IT-8, pp. 21-28, Jan. 1962.
2. M. P. C. Fossorier, "Quasi-cyclic low-density parity-check codes from circulant permutation matrices," IEEE Trans. on Inf. Theory, vol. 50, no. 8, pp. 1788-1793, Aug. 2004.
3. H. Zhong and T. Zhang, "Block-LDPC: a practical LDPC coding system design approach," IEEE Trans. on Circuits and Systems I, vol. 52, no. 4, pp. 766-775, Apr. 2005.
4. Y. Sun, M. Karkooti, and J. R. Cavallaro, "High throughput, parallel, scalable LDPC encoder/decoder architecture for OFDM systems," in Proc. IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software, Oct. 2006, pp. 39-42.
5. K. K. Gunnam, G. S. Choi, W. Wang, E. Kim, and M. B. Yeary, "Decoding of quasi-cyclic LDPC codes using an on-the-fly computation," in Proc. Fortieth Asilomar Conference on Signals, Systems and Computers, Oct. 2006, pp. 1192-1199.
6. K. K. Gunnam, G. S. Choi, W. Wang, and M. B. Yeary, "Multi-rate layered decoder architecture for block ldpc codes of the ieee 802.11n wireless standard," in Proc. IEEE International Symposium on Circuits and Systems, May 2007, pp. 1645-1648.
7. Digital Video Broadcasting (DVB) User guidelines for the second generation system for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications (DVB-S2), ETSI TR 102 376, Feb. 2005.
8. IEEE P802.16e, Part 16, "Air Interface for Fixed and Mobile Broadband Wireless Access Systems," Amendment 2: Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands, and Corrigendum 1, Feb. 2006.
9. IEEE P802.11n/D5.02, Part 11, "Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: Enhancements for Higher Throughput", July 2008.
10. S. Sharon, J. Litsyn, and J. Goldberger, "An efficient message-passing schedule for LDPC decoding," in Proc. 23rd IEEE Convention of Electrical and Electronics Engineers in Israel, Sept. 2004, pp. 223-226.
11. F. R. Kschischang, B. J. Frey, and H.-A. Loeliger, "Factor graphs and the sum-product algorithm," IEEE Trans. on Inf. Theory, vol. 47, no. 2, pp. 498-519, Feb. 2001.
12. A. J. Blanksby and C. J. Howland, "A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder," vol. 37, no. 3, pp. 404-412, Mar. 2002.
13. X.-Y. Shih, C.-Z. Zhan, C.-H. Lin, and A.-Y. Wu, "An 8.29mm2 52mW multi-mode LDPC decoder design for mobile WiMAX system in 0.13um CMOS process," vol. 43, no. 3, pp. 672-683, Mar. 2008.
14. S. Sharon, J. Litsyn, and J. Goldberger, "Efficient serial message-passing schedulers for LDPC decoding," IEEE Trans. on Inf. Theory, vol. 53, no. 11, pp. 4076-4091, Nov. 2007.
15. J. Chen, A. Dholakia, E. Eleftheriou, M. P. C. Fossorier, and X.-Y. Hu, "Reduced-complexity decoding of LDPC codes," IEEE Trans. on Comm., vol. 53, no. 7, pp. 1288-1299, Aug. 2005.
16. C.-H. Liu, C.-C. Lin, H.-C. Chang, C.-Y. Lee, and Y. Hsua, "Multi-mode message passing switch networks applied for QC-LDPC decoder," in IEEE International Symposium on Circuits and Systems, May 2008, pp. 752-755.
17. M. Rovini, G. Gentile, F. Rossi, and L. Fanucci, "A scalable decoder architecture for IEEE 802.11n LDPC codes," in Proc. IEEE GLOBECOM, Nov. 2007, pp. 3270-3274.