-
1
-
-
0012582658
-
Industrial applications of soft computing: A review
-
Sept
-
Y. Dote and S.J. Ovaska, "Industrial Applications of Soft Computing: A Review," Proc. IEEE, vol. 89, no. 9, pp. 1243-1265, Sept. 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.9
, pp. 1243-1265
-
-
Dote, Y.1
Ovaska, S.J.2
-
2
-
-
0035706021
-
Soft digital signal processing
-
DOI 10.1109/92.974895, PII S1063821001074212
-
R. Hegde and N.R. Shanbhag, "Soft Digital Signal Processing," IEEE Trans. Very Large Scale Integration Systems, vol. 9, no. 6, pp. 813-823, Dec. 2001. (Pubitemid 34126213)
-
(2001)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.9
, Issue.6
, pp. 813-823
-
-
Hegde, R.1
Shanbhag, N.R.2
-
3
-
-
25844483771
-
Energy aware computing through probabilistic switching: A study of limits
-
DOI 10.1109/TC.2005.145
-
K.V. Palem, "Energy Aware Computing through Probabilistic Switching: A Study of Limits," IEEE Trans. Computers, vol. 54, no. 9, pp. 1123-1137, Sept. 2005. (Pubitemid 41387741)
-
(2005)
IEEE Transactions on Computers
, vol.54
, Issue.9
, pp. 1123-1137
-
-
Palem, K.V.1
-
4
-
-
38149093277
-
Serial addition: Locally connected architectures
-
Nov
-
V. Beiu, S. Aunet, J. Nyathi, R.R. Rydberg III, and W. Ibrahim, "Serial Addition: Locally Connected Architectures," IEEE Trans. Circuits and Systems I, vol. 54, no. 11, pp. 2564-2579, Nov. 2007.
-
(2007)
IEEE Trans. Circuits and Systems i
, vol.54
, Issue.11
, pp. 2564-2579
-
-
Beiu, V.1
Aunet, S.2
Nyathi, J.3
Rydberg III, R.R.4
Ibrahim, W.5
-
5
-
-
14844364412
-
Addition related arithmetic operations via controlled transport of charge
-
DOI 10.1109/TC.2005.40
-
S. Cotofana, C. Lageweg, and S. Vassiliadis, "Addition Related Arithmetic Operations via Controlled Transport of Charge," IEEE Trans. Computers, vol. 54, no. 3, pp. 243-256, Mar. 2005. (Pubitemid 40351844)
-
(2005)
IEEE Transactions on Computers
, vol.54
, Issue.3
, pp. 243-256
-
-
Cotofana, S.1
Lageweg, C.2
Vassiliadis, S.3
-
7
-
-
77951023589
-
Bio- inspired imprecise computational blocks for efficient vlsi implementation of soft-computing applications
-
Apr
-
H.R. Mahdiani, A. Ahmadi, S.M. Fakhraie, and C. Lucas, "Bio- Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications," IEEE Trans. Circuits and Systems I: Regular Papers, vol. 57, no. 4, pp. 850-862, Apr. 2010.
-
(2010)
IEEE Trans. Circuits and Systems I: Regular Papers
, vol.57
, Issue.4
, pp. 850-862
-
-
Mahdiani, H.R.1
Ahmadi, A.2
Fakhraie, S.M.3
Lucas, C.4
-
8
-
-
80052700256
-
Impact: Imprecise adders for low-power approximate computing
-
Aug
-
V. Gupta, D. Mohapatra, S.P. Park, A. Raghunathan, and K. Roy, "IMPACT: IMPrecise Adders for Low-Power Approximate Computing," Proc. Int'l Symp. Low Power Electronics and Design (ISLPED), pp. 1-3, Aug. 2011.
-
(2011)
Proc. Int'l Symp. Low Power Electronics and Design (ISLPED)
, pp. 1-3
-
-
Gupta, V.1
Mohapatra, D.2
Park, S.P.3
Raghunathan, A.4
Roy, K.5
-
9
-
-
38149102427
-
A probabilistic cmos switch and its realization by exploiting noise
-
Oct
-
S. Cheemalavagu, P. Korkmaz, K.V. Palem, B.E.S. Akgul, and L.N. Chakrapani, "A Probabilistic CMOS Switch and Its Realization by Exploiting Noise," Proc. IFIP Int'l Conf. VLSI SoC (IFIP-VLSI SoC), Oct. 2005.
-
(2005)
Proc. IFIP Int'l Conf. VLSI SoC (IFIP-VLSI SoC)
-
-
Cheemalavagu, S.1
Korkmaz, P.2
Palem, K.V.3
Akgul, B.E.S.4
Chakrapani, L.N.5
-
10
-
-
77953116122
-
A general mathematical model of probabilistic ripple-carry adders
-
M.S.K. Lau, K.V. Ling, Y.C. Chu, and A. Bhanu, "A General Mathematical Model of Probabilistic Ripple-Carry Adders," Proc. Conf. Design Automation Test Europe, pp. 1100-1105, 2010.
-
(2010)
Proc. Conf. Design Automation Test Europe
, pp. 1100-1105
-
-
Lau, M.S.K.1
Ling, K.V.2
Chu, Y.C.3
Bhanu, A.4
-
11
-
-
84855785059
-
On the reliable performance of sequential adders in soft computing
-
J. Liang, J. Han, and F. Lombardi, "On the Reliable Performance of Sequential Adders in Soft Computing," Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems, pp. 3-10, 2011.
-
(2011)
Proc. IEEE Int'l Symp. Defect and Fault Tolerance in VLSI Systems
, pp. 3-10
-
-
Liang, J.1
Han, J.2
Lombardi, F.3
-
12
-
-
49749100727
-
Variable latency speculative addition: A new paradigm for arithmetic circuit design
-
A.K. Verma, P. Brisk, and P. Ienne, "Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design," Prof. Conf. Design, Automation and Test in Europe (DATE), pp. 1250-1255, 2008.
-
(2008)
Prof. Conf. Design, Automation and Test in Europe (DATE)
, pp. 1250-1255
-
-
Verma, A.K.1
Brisk, P.2
Ienne, P.3
-
13
-
-
77950428071
-
An enhanced low-power high- speed adder for error tolerant application
-
N. Zhu, W.L. Goh, and K.S. Yeo, "An Enhanced Low-Power High- Speed Adder for Error Tolerant Application," Proc. 12th Int'l Symp. Integrated Circuits (ISIC), pp. 69-72, 2009.
-
(2009)
Proc. 12th Int'l Symp. Integrated Circuits (ISIC)
, pp. 69-72
-
-
Zhu, N.1
Goh, W.L.2
Yeo, K.S.3
-
15
-
-
40049089079
-
Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
-
article 8, Jan
-
S. Krishnaswamy, G.F. Viamontes, I.L. Markov, and J.P. Hayes, "Probabilistic Transfer Matrices in Symbolic Reliability Analysis of Logic Circuits," ACM Trans. Design Automation of Electronic Systems, vol. 13, article 8, Jan. 2008.
-
(2008)
ACM Trans. Design Automation of Electronic Systems
, vol.13
-
-
Krishnaswamy, S.1
Viamontes, G.F.2
Markov, I.L.3
Hayes, J.P.4
-
16
-
-
77953899290
-
Scalable and accurate estimation of probabilistic behavior in sequential circuits
-
C-C Yu and J.P. Hayes, "Scalable and Accurate Estimation of Probabilistic Behavior in Sequential Circuits," Proc. IEEE 28th VLSI Test Symp. (VTS), pp. 165-170, 2010.
-
(2010)
Proc. IEEE 28th VLSI Test Symp. (VTS)
, pp. 165-170
-
-
Yu, C.-C.1
Hayes, J.P.2
-
17
-
-
79551477506
-
Reliability evaluation of logic circuits using probabilistic gate models
-
J. Han, H. Chen, E. Boykin, and J. Fortes, "Reliability Evaluation of Logic Circuits Using Probabilistic Gate Models," Microelectronics Reliability, vol. 51, no. 2, pp. 468-476, 2011.
-
(2011)
Microelectronics Reliability
, vol.51
, Issue.2
, pp. 468-476
-
-
Han, J.1
Chen, H.2
Boykin, E.3
Fortes, J.4
-
18
-
-
77954473523
-
Stochastic computational models for accurate reliability evaluation of logic circuits
-
H. Chen and J. Han, "Stochastic Computational Models for Accurate Reliability Evaluation of Logic Circuits," Proc. 20th Great Lakes Symp. VLSI (GLSVLSI '10), pp. 61-66, 2010.
-
(2010)
Proc. 20th Great Lakes Symp. VLSI (GLSVLSI '10)
, pp. 61-66
-
-
Chen, H.1
Han, J.2
-
19
-
-
84881162111
-
Analysis of error masking and restoring properties of sequential circuits
-
to be published
-
J. Liang, J. Han, and F. Lombardi, "Analysis of Error Masking and Restoring Properties of Sequential Circuits," IEEE Trans. Computers, to be published, 2011.
-
(2011)
IEEE Trans. Computers
-
-
Liang, J.1
Han, J.2
Lombardi, F.3
-
21
-
-
24344467032
-
Toward hardware-redundant, fault-tolerant logic for nanoelectronics
-
DOI 10.1109/MDT.2005.97
-
J. Han, J. Gao, Y. Qi, P. Jonker, and J. Fortes, "Toward Hardware- Redundant, Fault-Tolerant Logic for Nanoelectronics," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 328-339, July/Aug. 2005. (Pubitemid 41249778)
-
(2005)
IEEE Design and Test of Computers
, vol.22
, Issue.4
, pp. 328-339
-
-
Han, J.1
Gao, J.2
Qi, Y.3
Jonker, P.4
Fortes, J.A.B.5
|