Scalable and accurate estimation of probabilistic behavior in sequential circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2010, Pages 165-170

  Yu, Chien Chih ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

Sequential circuits; Signal probability estimation; Simulation methods; Soft error models

Indexed keywords

ACCURATE ESTIMATION; CIRCUIT RELIABILITY; FAST AND ACCURATE SIMULATIONS; LOGIC LEVELS; PROBABILISTIC BEHAVIOR; SEQUENTIAL LOGIC; SIGNAL ERROR PROBABILITY; SIGNAL PROBABILITY; SIMULATION METHODS; SOFT ERROR; SOFT ERROR EFFECTS; SOFT ERROR MODELS;

COMPUTER SIMULATION; ESTIMATION; SEQUENTIAL CIRCUITS;

PROBABILITY;

EID: 77953899290     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2010.5469586     Document Type: Conference Paper

References (18)

1. M. Abramovici, P. R. Menon, and D. T. Miller: "Critical path tracing: an alternative to fault simulation," IEEE. Design & Test, pp. 83-93, 1984.
2. H. Asadi and M. B. Tahoori: "An analytical approach for soft error rate estimation in digital circuits," Proc. ISCAS, pp. 2991-2994, 2005.
3. H. Asadi and M. B. Tahoori: "Soft error modeling and protection for sequential elements," Proc. DFT, pp. 463-471, 2005.
4. H. Asadi and M. B. Tahoori: "Soft error derating computation in sequential circuits," Proc. ICCAD, pp. 497-501, 2006.
5. R. I. Bahar, J. Mundy and J. Chan: "A probabilistic based design methodology for nanoscale computation," Proc. ICCAD, pp. 480-486, 2003.
6. A. Dutta and N. A. Touba: "Iterative OPDD based signal probability calculation," Proc. VTS, pp. 72-77, 2006.
7. R. Kodavarti and M. R. Mercer: "Signal probability calculations using partial functional manipulations," Proc. VTS, pp. 194-200, 1993.
8. S. Krishnaswamy, I. L. Markov and J. P. Hayes: "Tracking uncertainty with probabilistic logic circuit testing," IEEE Design & Test, pp. 312-321, 2007.
9. S. Krishnaswamy, G. F. Viamontes, I. L. Markov and J. P. Hayes: "Accurate reliability evaluation and enhancement via probabilistic transfer matrices," Proc. DATE, pp. 282-287, 2005.
10. S. Krishnaswamy, G. F. Viamontes, I. L. Markov and J. P. Hayes: "Probabilistic transfer matrices in symbolic reliability analysis of logic circuits," ACM TODAES, vol. 13, Article No. 8, 2008.
11. N. Miskov-Zivanov and D. Marculescu: "MARS-S: modeling and reduction of soft errors in sequential circuits," Proc. ISQED, pp. 893-898, 2007.
12. N. Miskov-Zivanov and D. Marculescu: "Modeling and optimization for soft-error reliability of sequential circuits," IEEE Trans. CAD, pp. 803-816, 2008.
13. T. Rejimon and S. Bhanja: "An accurate probabilistic model for error detection," Proc. VLSI Design Conf., pp. 717-722, 2005.
14. S. J. Russell and P. Norvig: Artificial Intelligence - A Modern Approach, Prentice-Hall, 2001.
15. S. C. Seth and V. D. Agrawal: "PREDICT- probabilistic estimation of digital circuit reliability," Proc. FTCS, pp. 220-225, 1985.
16. T. Uchino, F. Minami, T. Mitsuhashi and N. Goto: "Switching activity analysis using Boolean approximation method," Proc. ICCAD, pp.20-25, 1995.
17. K. M. Zick and J. P. Hayes: "High-level vulnerability over space and time to insidious soft errors," Proc. HLDVT, pp. 161-168, 2008.
18. B. Zhang, W. S. Wang and M. Orshansky: "FASER: fast analysis of soft error susceptibility for cell-based designs," Proc. ISQED, pp. 27-29, 2006.