Stochastic computational models for accurate reliability evaluation of logic circuits

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 61-66

  Chen, Hao ^a   Han, Jie ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

fault tolerance; logic circuits; reliability evaluation; stochastic computation; stochastic computational model

Indexed keywords

ANALYTICAL APPROACH; BINARY BIT STREAM; CMOS TECHNOLOGY; COMPUTATIONAL APPROACH; COMPUTATIONAL METHODOLOGY; COMPUTATIONAL MODEL; LARGE CIRCUITS; RANDOM FLUCTUATION; RELIABILITY EVALUATION; SIMULATION RESULT; STOCHASTIC COMPUTATION; VLSI DESIGN;

CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK ANALYSIS; FAULT TOLERANCE; LAKES; QUALITY ASSURANCE; STOCHASTIC MODELS; STOCHASTIC SYSTEMS; SWITCHING CIRCUITS;

LOGIC CIRCUITS;

EID: 77954473523     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785497     Document Type: Conference Paper

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