IMPACT: IMPrecise adders for low-power approximate computing

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 409-414

  Gupta, Vaibhav ^a   Mohapatra, Debabrata ^a   Park, Sang Phill ^a   Raghunathan, Anand ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

Approximate computing; Low power; Mirror adder

Indexed keywords

ALTERNATIVE APPROACH; APPROXIMATE COMPUTING; AREA SAVINGS; ARITHMETIC UNIT; CRITICAL PATHS; DESIGN ARCHITECTURE; FULL ADDERS; HUMAN SENSE; IMAGE COMPRESSION ALGORITHMS; LOGIC COMPLEXITY; LOW POWER; MULTI-BITS; MULTIMEDIA APPLICATIONS; MULTIMEDIA DEVICE; NUMERICAL ACCURACY; NUMERICAL OUTPUT; OUTPUT QUALITY; POST LAYOUT SIMULATION; POWER SAVINGS; REDUCED COMPLEXITY; SIGNAL PROCESSING ALGORITHMS; TRANSISTOR LEVEL; VOLTAGE-SCALING;

ALGORITHMS; DESIGN; IMAGE COMPRESSION; LOW POWER ELECTRONICS; MULTIMEDIA SIGNAL PROCESSING; POWER ELECTRONICS;

ADDERS;

EID: 80052700256     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993675     Document Type: Conference Paper

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