Reliability evaluation of logic circuits using probabilistic gate models

Microelectronics Reliability

Volumn 51, Issue 2, 2011, Pages 468-476

  Han, Jie ^a   Chen, Hao ^a   Boykin, Erin ^b   Fortes, José ^b  

^a UNIVERSITY OF ALBERTA   (Canada)

^b University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATE ALGORITHMS; BENCHMARK CIRCUIT; CIRCUIT RELIABILITY; COMPUTATIONAL ALGORITHM; DESIGN FLOWS; GATE MODELS; LARGE CIRCUITS; LOGIC MODULE; MANUFACTURING CONSTRAINT; MODULAR APPROACH; NANOSCALE TECHNOLOGIES; NUMBER OF GATES; RECONVERGENT FAN-OUTS; RELIABILITY EVALUATION; SIMULATION RESULT; WORST-CASE COMPLEXITY;

ALGORITHMS; BENCHMARKING; COMPUTATIONAL COMPLEXITY; INFORMATION DISSEMINATION; LOGIC DEVICES; NANOTECHNOLOGY; PROBABILISTIC LOGICS; PROBABILITY; RELIABILITY; SWITCHING CIRCUITS;

LOGIC CIRCUITS;

EID: 79551477506     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.07.154     Document Type: Conference Paper

References (30)

1. S. Borkar Designing reliable systems from unreliable components: the challenges of transistor variability and degradation IEEE Micro 25 6 2005 10 16
2. B.P. Wong, A. Mittal, Y. Cao, and G. Starr Nano-CMOS circuit and physical design 2005 John Wiley & Sons Hoboken
3. C. Constantinescu Trends and challenges in VLSI circuit reliability IEEE Micro 2003 14 19
4. International Technology Roadmap for Semiconductors; 2009. < http://public.itrs.net/ >.
5. Shanbhag NR, Mitra S, de Veciana G, Orshansky M, Marculescu R, Roychowdhury J, Jones D, Rabaey JM. The search for alternative computational paradigms. The special issue on "System IC Design Challenges beyond 32 nm". IEEE Des Test Comput 2008;25(4).
6. J. von Neumann Probabilistic logics and the synthesis of reliable organisms from unreliable components C.E. Shannon, J. McCarthy, Automata studies 1956 Princeton University Press Princeton (NJ) 43 98
7. Siewiorek DP, Swarz RS. Reliable computer systems: design and evaluation. Natick (MA, USA): AK Peters; 1998.
8. S.K. Shukla, R.I. Bahar, Nano, quantum and molecular computing: implications to high level design and validation 2004 Kluwer Academic Publishers Boston
9. K.P. Parker, and E.J. McCluskey Probabilistic treatment of general combinational networks IEEE Trans Comput C 24 1975 668 670
10. S.C. Bass, and J.W. Grundmann Expected value analysis of combinational logic networks IEEE Trans Circuits Syst 28 5 1981
11. Bahar RI, Chen J, Mundy J. A probabilistic-based design methodology for nanoscale computation. In: Proceedings of international conference on computer aided design, San Jose, CA, November 2003. p. 480-6.
12. Bhaduri D, Shukla S. Nanoprism: a tool for evaluating granularity versus reliability tradeoffs in nano architectures. In: ACM GLSVLSI, Boston, MA, April 2004.
13. S. Krishnaswamy, G.F. Viamontes, I.L. Markov, and J.P. Hayes Probabilistic transfer matrices in symbolic reliability analysis of logic circuits ACM Trans Des Autom Electron Syst 13 1#8 2008
14. T. Rejimon, K. Lingasubramanian, and S. Bhanja Probabilistic error modeling for nano-domain logic circuits IEEE Trans VLSI 17 1 2009 55 65
15. M.R. Choudhury, and K. Mohanram Reliability analysis of logic circuits IEEE Trans CAD 28 3 2009 392 405
16. Abdollahi A. Probabilistic decision diagrams for exact probabilistic analysis. In: Proc of IEEE/ACM intl conference on computer aided design; 2007. p. 266-72.
17. Mohyuddin N, Pakbaznia E, Pedram M. Probabilistic error propagation in logic circuits using the Boolean difference calculus. In: IEEE intl conf on comp des, Lake Tahoe, CA, USA; 2008. p. 7-13.
18. D.T. Franco, M.C. Vasconcelos, L. Naviner, and J.-F. Naviner Signal probability for reliability evaluation of logic circuits Microelectron Reliab 48 8-9 2008 1586 1591
19. Sivaswamy S, Bazargan K, Riedel M. Estimation and optimization of reliability of noisy digital circuits. In: International symposium on quality electronic design, San Jose, CA, USA; 2009. p. 213-9.
20. S.J. Seyyed Mahdavi, and K. Mohammadi SCRAP: sequential circuits reliability analysis program Microelectron Reliab 49 8 2009 924 933
21. J. Han, and P. Jonker A system architecture solution for unreliable nanoelectronic devices IEEE Trans Nanotechnol 1 4 2002 201 208
22. Y. Qi, J.B. Gao, and J.A.B. Fortes Markov chains and probabilistic computation - a general framework for multiplexed nanoelectronic systems IEEE Trans Nanotechnol 4 2 2005 194 205
23. S. Roy, and V. Beiu Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures IEEE Trans Nanotechnol 4 4 2005 441 451
24. J. Han, J. Gao, Y. Qi, P.P. Jonker, and J.A.B. Fortes Toward hardware-redundant, fault-tolerant logic for nanoelectronics IEEE Des Test Comput 22 4 2005 328 339
25. Anghel L, Nicolaidis M. Defects tolerant logic gates for unreliable future nanotechnologies. In: Sandoval F et al., editors. Lecture notes in computer science. IWANN 2007 4507; 2007. p. 422-9.
26. 2-transistor structure for reliable nanoelectronic designs IET Comput Digit Tech 3 6 2009 570 580
27. Han J, Taylor ER, Gao J, Fortes JAB. Faults, error bounds and reliability of nanoelectronic circuits. In: Proc. IEEE ASAP 2005; 2005. p. 247-53.
28. Taylor ER, Han J, Fortes JAB. Towards accurate and efficient reliability modeling of nanoelectronic circuits. In: Proc IEEE-NANO 2006. IEEE conference on nanotechnology.
29. M.C. Hansen, H. Yalcin, and J.P. Hayes Unveiling the ISCAS-85 benchmarks: a case study in reverse engineering IEEE Des Test Comput 16 3 1999 72 80
30. M.L. Bushnell, and V.D. Agrawal Essentials of electronic testing 2005 Springer Boston