Accelerating FPGA routing using architecture-adaptive A* techniques

Proceedings - 2005 IEEE International Conference on Field Programmable Technology

Volumn 2005, Issue , 2005, Pages 225-232

  Sharma, Akshay ^a   Hauck, Scott ^b  

^a Actel Corp   (United States)

^b UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE SYSTEMS; COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; HEURISTIC METHODS; HIERARCHICAL SYSTEMS; MOTION PLANNING; MEMORY ARCHITECTURE;

HIERARCHICAL ARCHITECTURE; MEMORY IMPROVEMENTS; PATH FINDING TECHNIQUE; ROUTING RUNTIMES;

ROUTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

A* ALGORITHM; ARCHITECTURE-ADAPTIVE; HEURISTIC TECHNIQUES; HIERARCHICAL ARCHITECTURES; PATH FINDING; ROUTINGS; RUNTIMES; SPEED UP;

EID: 33846576911     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2005.1568551     Document Type: Conference Paper

References (12)

1. V. Betz, J. Rose and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs, Kluwer Academic Publishers, Boston MA, 1999.
2. G. Boriello, C. Ebeling, S Hauck, and S. Burns, "The Triptych FPGA Architecture", IEEE Transactions on VLS Systems Vol. 3 No. 4, IEEE, New York NY, 1995, pp. 473-482.
3. K. Compton, A. Sharma, S. Phillips, and S. Hauck, "Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems", International Conference on Field Programmable Logic and Applications, Springer-Verlag, New York NY, 2002, pp. 59-68.
4. K. Compton, S. Hauck, "Totem: Custom Reconfigurable Array Generation", IEEE Symposium on FPGAs for Custom Computing Machines, IEEE, New York NY, 2001.
5. T.H. Cormen, C.E. Leiserson, and R.L. Rivest, Introduction to Algorithms, MIT Press, Cambridge MA, 1990.
6. A. DeHon, "Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why you don't really want 100% LUT utilization)", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM Press, New York NY, 1999, pp. 69-78.
7. A. Marquardt, V. Betz and J. Rose, "Speed and Area Tradeoffs in Cluster-Based FPGA Architectures", IEEE Transactions on VLSI Systems Vol. 8 No. 1, IEEE, New York NY, 2000, pp. 84-93.
8. L. McMurchie, and C. Ebeling, "PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs", ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM Press, New York NY, 1995, pp 111-117.
9. N. Nilsson, Principles of Artificial Intelligence, Morgan Kaufmann, San Francisco CA, 1980.
10. A Sharma, C. Ebeling, and S. Hauck, "Architecture-Adaptive Routability-Driven Placement for FPGAs", in International Conference on Field Programmable Logic and Applications, 2005.
11. J. Swartz, V. Betz and J. Rose, "A Fast Routability-Driven Router for FPGAs", ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ACM Press, New York NY, 1998, pp. 140-149.
12. R. Tessier, "Negotiated A* Routing for FPGAs", Fifth Canadian Workshop on Field Programmable Devices, 1998.