CMOS-integrated memristors for neuromorphic architectures

2011 International Semiconductor Device Research Symposium, ISDRS 2011

Volumn , Issue , 2011, Pages

  Wheeler, Dana ^a   Kim, Kuk Hwan ^b   Gaba, Siddharth ^b   Wang, Eason ^a   Kim, Sam ^a   Valles, Irma ^a   Li, James ^a   Royter, Yakov ^a   Cruz Albrecht, Jose ^a   Hussain, Tahir ^a   Lu, Wei ^b   Srinivasa, Narayan ^a  

^a Hughes Aircraft Co   (United States)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG MEMORIES; BIT DENSITY; CMOS WAFERS; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; CROSS BAR; CURRENT RATIOS; EFFECTIVE NUMBER OF BITS; ELECTRICAL DATA; HIGH-DENSITY; MEMRISTOR; NEUROMORPHIC; NEUROMORPHIC CIRCUITS; PROBE PADS; RECTIFYING BEHAVIORS; RESISTANCE STATE;

FABRICATION; MEMORY ARCHITECTURE; PASSIVE FILTERS; RESISTORS;

MEMRISTORS;

EID: 84863150015     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISDRS.2011.6135279     Document Type: Conference Paper

References (2)

1. S. H. Jo and W. Lu, "CMOS Compatible Nanoscale Nonvolatile Resistance Switching Memory," Nano Letters, vol. 8, no. 2, pp. 392-397, January 2008.
2. K. Minkovich, et al., "Programming Time-Multiplexed Reconfigurable Hardware using a Scalable Neuromorphic Compiler," IEEE Transactions on Neural Networks (currently under review)