Demonstration of a subthreshold FPGA using monolithically integrated graphene interconnects

IEEE Transactions on Electron Devices

Volumn 60, Issue 1, 2013, Pages 383-390

  Lee, Kyeong Jae ^a,b   Park, Hyesung ^a   Kong, Jing ^a   Chandrakasan, Anantha P ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

^b SAMSUNG Electronics   (South Korea)

Author keywords

CMOS integrated circuits; graphene; interconnects

Indexed keywords

ALUMINUM WIRES; INTERCONNECT FABRICS; LOW SWING; MONOLITHICALLY INTEGRATED; SUBTHRESHOLD; SYSTEM APPLICATIONS;

CAPACITANCE; CMOS INTEGRATED CIRCUITS; OPTICAL INTERCONNECTS; POWER ELECTRONICS; WIRE;

GRAPHENE;

EID: 84871800961     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2225150     Document Type: Article

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