A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Ryan, Joseph F ^a   Calhoun, Benton H ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; GLOBAL INTERCONNECTS; LOW SWING; SUBTHRESHOLD;

INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 78649857811     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617466     Document Type: Conference Paper

References (6)

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6. J. F. Ryan and B. H. Calhoun, "Minimizing Offset for Latching Voltage-Mode Sense Amplifiers for Sub-threshold Operation," ISQED, 2008.