An energy-efficient subthreshold level converter in 130-nm CMOS

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 57, Issue 4, 2010, Pages 290-294

  Wooters, Stuart N ^a   Calhoun, Benton H ^a   Blalock, Travis N ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

Level converter; Level up shifter; Subthreshold

Indexed keywords

CMOS INTEGRATED CIRCUITS; VOLTAGE SCALING;

CURRENT CHARACTERISTIC; ENERGY EFFICIENT; LEVEL CONVERTER; LEVEL-UP SHIFTERS; MEASURED RESULTS; SUB-THRESHOLD CIRCUITS; SUBTHRESHOLD; SUBTHRESHOLD VOLTAGES;

ENERGY EFFICIENCY;

EID: 77951666640     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2043471     Document Type: Article

References (13)

1. H. Soeleman and K. Roy, "Ultra-low power digital subthreshold logic circuits," in Proc. ISPLED, 1999, pp. 94-96.
2. A. Wang, A. Chandrakasan, and S. Kosonocky, "Optimal supply and threshold scaling for subthreshold CMOS circuits," in Proc. IEEE Comput. Soc. Annu. Symp. VLSI, 2002, pp. 5-9.
3. K.-H. Koo, J.-H. Seo, M.-L. Ko, and J.-W. Kim, "A new level-up shifter for high speed and wide range interface in ultra deep sub-micron," in Proc. ISCAS, May 2005, vol. 2, pp. 1063-1065.
4. B. Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester, and D. Blaauw, "Energy- efficient subthreshold processor design," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 8, pp. 1127-1137, Aug. 2009.
5. I. J. Chang, J.-J. Kim, and K. Roy, "Robust level converter design for sub-threshold logic," in Proc. ISLPED, 2006, pp. 14-19.
6. Y.-S. Lin and D. M. Sylvester, "Single stage static level shifter design for subthreshold to I/O voltage conversion," in Proc. ISLPED, 2008, pp. 197-200.
7. A. Chavan and E. MacDonald, "Ultra low voltage level shifters to interface sub and super threshold reconfigurable logic cells," in Proc. IEEE Aerosp. Conf., Mar. 2008, pp. 1-6.
8. H. Shao and C.-Y. Tsui, "A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic," in Proc. 33rd ESSCIRC, Sep. 2007, pp. 312-315.
9. t microcontroller with integrated SRAM and switched capacitor DC-DC converter," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 115-126, Jan. 2009.
10. S. Hanson, M. Seok, Y.-S. Lin, Z. Y. Foo, D. Kim, Y. Lee, N. Liu, D. Sylvester, and D. Blaauw, "A low-voltage processor for sensing applications with picowatt standby mode," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1145-1155, Apr. 2009.
11. S. C. Jocke, J. F. Bolus, S. N. Wooters, A. D. Jurik, A. C. Weaver, T. N. Blalock, and B. H. Calhoun, "A 2.6-μw sub-threshold mixed-signal ECG SOC," in Proc. Symp. VLSI Circuits, Jun. 2009, pp. 60-61.
12. A. Wang and A. Chandrakasan, "A 180-MV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
13. J. Chen, L. Clark, and T.-H. Chen, "An ultra-low-power memory with a subthreshold power supply voltage," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2344-2353, Oct. 2006.