Low-swing signaling on monolithically integrated global graphene interconnects

IEEE Transactions on Electron Devices

Volumn 57, Issue 12, 2010, Pages 3418-3425

  Lee, Kyeong Jae ^a   Qazi, Masood ^a   Kong, Jing ^a   Chandrakasan, Anantha P ^a  

^a Department of Electrical Engineering and Computer Science   (United States)

Author keywords

complementary metal oxide semiconductor (CMOS) integrated circuits; graphene; interconnects; low swing signaling

Indexed keywords

CMOS CHIPS; COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) INTEGRATED CIRCUITS; DATA-COMMUNICATION; GRAPHENE SHEETS; GRAPHENES; HIGH-SHEET-RESISTANCE; INTERCONNECTS; LOW-SWING SIGNALING; MONOLITHICALLY INTEGRATED; NARROW WIRES; PSEUDO-RANDOM BINARY SEQUENCES; TEST CHIPS; TOTAL ENERGY; VOLTAGE SWINGS;

BINARY SEQUENCES; CHEMICAL VAPOR DEPOSITION; DIELECTRIC DEVICES; ELECTRIC CONVERTERS; ELECTRIC RESISTANCE; GRAPHENE; INTEGRATED CIRCUITS; SEMICONDUCTOR GROWTH; SIGNALING; WIRE;

CMOS INTEGRATED CIRCUITS;

EID: 78650005333     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2083667     Document Type: Article

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