A 320 mV 56 W 411 GOPS/watt ultra-low voltage motion estimation accelerator in 65 nm CMOS

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 1, 2009, Pages 107-114

  Kaul, Himanshu ^a   Anders, Mark A ^a   Mathew, Sanu K ^a   Hsu, Steven K ^a   Agarwal, Amit ^a   Krishnamurthy, Ram K ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Motion estimation; Sum of absolute difference (SAD); Ultra low voltage; Variation compensation; Video encoding

Indexed keywords

COMPRESSORS; ENCODING (SYMBOLS); ENERGY EFFICIENCY; INTEGRATED CIRCUIT LAYOUT;

MOBILE MICROPROCESSORS; OUTPUT LEVELS; PERFORMANCE VARIATIONS; REAL-TIME VIDEOS; SCALABLE PERFORMANCES; SUBTHRESHOLD OPERATIONS; SUM OF ABSOLUTE DIFFERENCE (SAD); SUM OF ABSOLUTE DIFFERENCES; SUPPLY VOLTAGES; TEMPERATURE INDUCED; ULTRA-LOW VOLTAGE; VARIATION COMPENSATION; VIDEO ENCODING;

MOTION ESTIMATION;

EID: 58149229436     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.2007164     Document Type: Conference Paper

References (14)

1. H.-C. Chang et al., "A 7 mW-to-183 mW dynamic quality-scalable H.264 video encoder chip," in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 280-281.
2. C.-P. Lin et al., "A 5 mW MPEG4 SP encoder with 2D bandwidthsharing motion estimation for mobile applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 412-413.
3. 2 1080p H.264/AVC high-profile encoder chip," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 314-315.
4. H. Yamauchi et al., "An 81 MHz, 1280 × 720 pixels × 30 frames/s MPEG-4 video/audio codec processor," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 130-131.
5. Y.-W. Huang et al., "A 1.3 TOPS H.264/AVC single-chip encoder for HDTV applications," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 128-129.
6. T. Fujiyoshi et al., "An H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic voltage/frequency scaling," in IEEE ISSCC Dig. Tech. Papers, Feb. 2005, pp. 132-133.
7. A. Wang and A. Chandrakasan, "A 180-mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 310-319, Jan. 2005.
8. J. Kwong et al., "A 65 nm sub-Vt microcontroller with integrated SRAM and switched-capacitor DC-DC converter," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 318-319.
9. S. Hanson et al., "Exploring variability and performance in a sub-200-mV processor," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 881-891, Apr. 2008.
10. M.-E. Hwang et al., "A 85 mV 40 nW process-tolerant subthreshold 8×8 FIR filter in 130 nm technology," in Symp. VLSI Circuits, Jun. 2007, pp. 154-155.
11. H. Kaul et al., "A 320 mV 56 μW 411 GOPS/Watt ultra-low voltage motion estimation accelerator in 65 nm CMOS," in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 316-317.
12. 2 SRAM cell," in IEDM Tech. Dig., Dec. 2004, pp. 657-660.
13. R. McGowen et al., "Power and temperature control on a 90-nm Itanium family processor," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 229-237, Jan. 2006.
14. C. Kim et al., "An on-die CMOS leakage current sensor for measuring process variation in sub-90 nm generations," in Symp. VLSI Circuits, Jun. 2004, pp. 250-251.