Challenges regarding parallel connection of SiC JFETs

IEEE Transactions on Power Electronics

Volumn 28, Issue 3, 2013, Pages 1449-1463

  Peftitsis, Dimosthenis ^a   Baburske, Roman ^b   Rabkowski, Jacek ^a   Lutz, Josef ^b   Tolstoy, Georg ^a   Nee, Hans Peter ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^b CHEMNITZ UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

Junction field effect transistor (JFET); parallel connected switches; pinch off voltage; reverse breakdown voltage of the gate; silicon carbide (SiC)

Indexed keywords

CURRENT CAPABILITY; CURRENT RATING; DEVICE PARAMETERS; GATE CIRCUIT; GATE DRIVERS; GATE VOLTAGES; HIGH POWER CONVERTERS; JUNCTION FIELD-EFFECT TRANSISTORS; NORMALLY ON; ON-STATE RESISTANCE; PARALLEL CONNECTIONS; PARALLEL-CONNECTED; PARASITIC INDUCTANCES; PINCH OFF VOLTAGE; PINCHOFF; REVERSE BREAKDOWN VOLTAGE; SINGLE GATES; SWITCHING LOSS; SWITCHING PERFORMANCE; TEMPERATURE DEPENDENCE; TRANSFER CHARACTERISTICS;

ELECTRIC BREAKDOWN; ELECTRIC CONNECTORS; FIELD EFFECT TRANSISTORS; HETEROJUNCTION BIPOLAR TRANSISTORS; INDUCTANCE; SWITCHING;

SILICON CARBIDE;

EID: 84867808127     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2012.2206611     Document Type: Article

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