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Volumn , Issue , 2011, Pages 2405-2412

Characterization of a high temperature multichip SiC JFET-based module

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT UNBALANCE; DC-BUS VOLTAGES; DOUBLE PULSE; DYNAMIC PERFORMANCE; ELECTRICAL PERFORMANCE; GATE RESISTANCE; HIGH TEMPERATURE; MULTI-CHIP; ON-STATE RESISTANCE; PACKAGE PARASITICS; SHOOT-THROUGH; SHOTTKY BARRIER; STATIC CHARACTERISTIC; SUBSTRATE LAYOUT; SWITCHING ELEMENTS; SWITCHING LOSS; THREE-PHASE INVERTER;

EID: 81855206653     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECCE.2011.6064088     Document Type: Conference Paper
Times cited : (32)

References (25)
  • 1
    • 33646891147 scopus 로고    scopus 로고
    • Silicon carbide benefits and advantages for power electronics circuits and systems
    • DOI 10.1109/JPROC.2002.1021562, PII S0018921902055767
    • A. Elasser and T. P. Chow, "Silicon carbide benefits and advantages for power electronics circuits and systems," Proceeding of IEEE, vol. 90, no. 6, pp. 969-986, June 2002. (Pubitemid 43785870)
    • (2002) Proceedings of the IEEE , vol.90 , Issue.6 , pp. 969-986
    • Elasser, A.1    Chow, T.P.2
  • 20
    • 2342510205 scopus 로고    scopus 로고
    • Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics
    • Y. Xiao, H. Shah, T. P. Chow, and R. J. Gutmann, "Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics," IEEE Applied Power Electronics Conference, 2004, vol.1, pp. 516-521.
    • IEEE Applied Power Electronics Conference, 2004 , vol.1 , pp. 516-521
    • Xiao, Y.1    Shah, H.2    Chow, T.P.3    Gutmann, R.J.4
  • 22
    • 48349119938 scopus 로고    scopus 로고
    • Impact of source inductance on synchronous buck regulator FET shoot through performance
    • A. G. Black, "Impact of source inductance on synchronous buck regulator FET shoot through performance," IEEE Power Electronics Specialists Conference, 2007, pp. 981-986.
    • IEEE Power Electronics Specialists Conference, 2007 , pp. 981-986
    • Black, A.G.1
  • 23
    • 81855210166 scopus 로고    scopus 로고
    • http://www.siced.com/
  • 24
    • 34948878171 scopus 로고    scopus 로고
    • Power MOSFETs paralleling operation for high power high density converters
    • H. Wang and F. Wang, "Power MOSFETs paralleling operation for high power high density converters," IEEE Industry Applications Society Annual Meeting, 2006, vol. 5, pp. 2284-2289.
    • IEEE Industry Applications Society Annual Meeting, 2006 , vol.5 , pp. 2284-2289
    • Wang, H.1    Wang, F.2
  • 25
    • 33947170483 scopus 로고    scopus 로고
    • Gate circuit layout optimization of power module regarding transient current imbalance
    • September
    • C. Martin, J. Guichon, J. Schanen, and R. Pasterczyk, "Gate circuit layout optimization of power module regarding transient current imbalance," IEEE Trans. on Power Electronics, vol. 21, no. 5, September 2006, pp. 1176-1184.
    • (2006) IEEE Trans. on Power Electronics , vol.21 , Issue.5 , pp. 1176-1184
    • Martin, C.1    Guichon, J.2    Schanen, J.3    Pasterczyk, R.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.