-
1
-
-
0004072686
-
-
AddisonWesley, 2nd edition
-
A. V. Aho, M. S. Lam, R. Sethi, and J. D. Ullman. Compilers: Principles, Techniques, and Tools. AddisonWesley, 2nd edition, 2007.
-
(2007)
Compilers: Principles, Techniques, and Tools
-
-
Aho, A.V.1
Lam, M.S.2
Sethi, R.3
Ullman, J.D.4
-
3
-
-
63549095070
-
The parsec benchmark suite: Characterization and architectural implications
-
C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In PACT '08.
-
PACT '08
-
-
Bienia, C.1
Kumar, S.2
Singh, J.P.3
Li, K.4
-
4
-
-
84859464490
-
The gem5 simulator
-
Aug
-
N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu, J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell, M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39:1-7, Aug. 2011.
-
(2011)
SIGARCH Comput. Archit. News
, vol.39
, pp. 1-7
-
-
Binkert, N.1
Beckmann, B.2
Black, G.3
Reinhardt, S.K.4
Saidi, A.5
Basu, A.6
Hestness, J.7
Hower, D.R.8
Krishna, T.9
Sardashti, S.10
Sen, R.11
Sewell, K.12
Shoaib, M.13
Vaish, N.14
Hill, M.D.15
Wood, D.A.16
-
5
-
-
84886049933
-
Software-based transparent and comprehensive control-flow error detection
-
E. Borin, C.Wang, Y.Wu, and G. Araujo. Software-based transparent and comprehensive control-flow error detection. In CGO '06.
-
CGO '06
-
-
Borin, E.1
Wang, C.2
Wu, Y.3
Araujo, G.4
-
6
-
-
84863493418
-
Automatic instruction-level software-only recovery
-
J. Chang, G. A. Reis, and D. I. August. Automatic instruction-level software-only recovery. In DSN '06.
-
DSN '06
-
-
Chang, J.1
Reis, G.A.2
August, D.I.3
-
7
-
-
0004116989
-
-
The MIT Press, 2nd edition
-
T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein. Introduction to Algorithms. The MIT Press, 2nd edition, 2001.
-
(2001)
Introduction to Algorithms
-
-
Cormen, T.H.1
Leiserson, C.E.2
Rivest, R.L.3
Stein, C.4
-
9
-
-
77954968857
-
Relax: An architectural framework for software recovery of hardware faults
-
M. de Kruijf, S. Nomura, and K. Sankaralingam. Relax: An architectural framework for software recovery of hardware faults. In ISCA '10, 2010.
-
(2010)
ISCA '10
-
-
De Kruijf, M.1
Nomura, S.2
Sankaralingam, K.3
-
11
-
-
84943385246
-
The transmeta code morphing software: Using speculation, recovery, and adaptive retranslation to address reallife challenges
-
J. C. Dehnert, B. K. Grant, J. P. Banning, R. Johnson, T. Kistler, A. Klaiber, and J. Mattson. The Transmeta code morphing software: Using speculation, recovery, and adaptive retranslation to address reallife challenges. In CGO '03.
-
CGO '03
-
-
Dehnert, J.C.1
Grant, B.K.2
Banning, J.P.3
Johnson, R.4
Kistler, T.5
Klaiber, A.6
Mattson, J.7
-
12
-
-
84863372488
-
Encore: Low-cost, fine-grained transient fault recovery
-
S. Feng, S. Gupta, A. Ansari, S. Mahlke, and D. August. Encore: Low-cost, fine-grained transient fault recovery. In MICRO '11.
-
MICRO ' 11
-
-
Feng, S.1
Gupta, S.2
Ansari, A.3
Mahlke, S.4
August, D.5
-
14
-
-
84866363636
-
Precise exception semantics in dynamic compilation
-
M. Gschwind and E. R. Altman. Precise exception semantics in dynamic compilation. In CC '02.
-
CC '02
-
-
Gschwind, M.1
Altman, E.R.2
-
15
-
-
35349016809
-
Complexity and exact algorithms for vertex multicut in interval and bounded treewidth graphs
-
J. Guo, F. HÃijffner, E. Kenar, R. Niedermeier, and J. Uhlmann. Complexity and exact algorithms for vertex multicut in interval and bounded treewidth graphs. European Journal of Operational Research, 186(2):542-553, 2008.
-
(2008)
European Journal of Operational Research
, vol.186
, Issue.2
, pp. 542-553
-
-
Guo, J.1
Hãijffner, F.2
Kenar, E.3
Niedermeier, R.4
Uhlmann, J.5
-
16
-
-
34547478253
-
Implementing virtual memory in a vector processor with software restart markers
-
M. Hampton and K. Asanovi'c. Implementing virtual memory in a vector processor with software restart markers. In ICS '06.
-
ICS '06
-
-
Hampton, M.1
Asanovi'c, K.2
-
19
-
-
33748522708
-
Exploiting reference idempotency to reduce speculative storage overflow
-
September
-
S. W. Kim, C.-L. Ooi, R. Eigenmann, B. Falsafi, and T. N. Vijaykumar. Exploiting reference idempotency to reduce speculative storage overflow. ACM Trans. Program. Lang. Syst., 28:942-965, September 2006.
-
(2006)
ACM Trans. Program. Lang. Syst.
, vol.28
, pp. 942-965
-
-
Kim, S.W.1
Ooi, C.-L.2
Eigenmann, R.3
Falsafi, B.4
Vijaykumar, T.N.5
-
20
-
-
3042658703
-
Llvm: A compilation framework for lifelong program analysis & transformation
-
C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO '04.
-
CGO '04
-
-
Lattner, C.1
Adve, V.2
-
21
-
-
0029208695
-
Compilerbased multiple instruction retry
-
C.-C. J. Li, S.-K. Chen, W. K. Fuchs, and W.-M. W. Hwu. Compilerbased multiple instruction retry. IEEE Transactions on Computers, 44(1):35-46, 1995.
-
(1995)
IEEE Transactions on Computers
, vol.44
, Issue.1
, pp. 35-46
-
-
J. Li, C.-C.1
Chen, S.-K.2
Fuchs, W.K.3
W. Hwu, W.-M.4
-
22
-
-
0025625415
-
Catch-compiler-Assisted techniques for checkpointing
-
C.-C. J. Li and W. K. Fuchs, CATCH-Compiler-Assisted techniques for checkpointing. In FTCS '90.
-
FTCS '90
-
-
J. Li, C.-C.1
Fuchs, W.K.2
-
24
-
-
41349107838
-
Argus: Low-cost comprehensive error detection in simple cores
-
A. Meixner, M. E. Bauer, and D. J. Sorin. Argus: Low-cost comprehensive error detection in simple cores. IEEE Micro, 28(1):52-59, 2008.
-
(2008)
IEEE Micro
, vol.28
, Issue.1
, pp. 52-59
-
-
Meixner, A.1
Bauer, M.E.2
Sorin, D.J.3
-
25
-
-
84864857149
-
Igpu: Exception support and speculative execution on gpus
-
J. Menon, M. de Kruijf, and K. Sankaralingam. iGPU: Exception support and speculative execution on GPUs. In ISCA '12, 2012.
-
(2012)
ISCA '12
-
-
Menon, J.1
De Kruijf, M.2
Sankaralingam, K.3
-
26
-
-
0036507790
-
Error detection by duplicated instructions in super-scalar processors
-
March
-
N. Oh, P. Shirvani, and E. McCluskey. Error detection by duplicated instructions in super-scalar processors. Reliability, IEEE Transactions on, 51(1):63-75, March 2002.
-
(2002)
Reliability IEEE Transactions On
, vol.51
, Issue.1
, pp. 63-75
-
-
Oh, N.1
Shirvani, P.2
McCluskey, E.3
-
27
-
-
0033077475
-
Memory exclusion: Optimizing the performance of checkpointing systems
-
J. S. Plank, Y. Chen, K. Li, M. Beck, and G. Kingsley. Memory exclusion: Optimizing the performance of checkpointing systems. Software-Practice & Experience, 29(2):125-142, 1999.
-
(1999)
Software-Practice & Experience
, vol.29
, Issue.2
, pp. 125-142
-
-
Plank, J.S.1
Chen, Y.2
Li, K.3
Beck, M.4
Kingsley, G.5
-
28
-
-
84873532234
-
Speculative lock elision: Enabling highly concurrent multithreaded execution
-
R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In MICRO '01.
-
MICRO '01
-
-
Rajwar, R.1
Goodman, J.R.2
-
30
-
-
27544438520
-
Design and evaluation of hybrid fault-detection systems
-
G. A. Reis, J. Chang, N. Vachharajani, R. Rangan, D. I. August, and S. S. Mukherjee. Design and evaluation of hybrid fault-detection systems. In ISCA '05, pages 148-159.
-
ISCA'05
, pp. 148-159
-
-
Reis, G.A.1
Chang, J.2
Vachharajani, N.3
Rangan, R.4
August, D.I.5
Mukherjee, S.S.6
-
32
-
-
0032667728
-
Ibm's s/390 g5 microprocessor design
-
T. J. Slegel et al. IBM's S/390 G5 microprocessor design. IEEE Micro, 19(2):12-23, 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.2
, pp. 12-23
-
-
Slegel, T.J.1
-
33
-
-
0024013595
-
Implementing precise interrupts in pipelined processors
-
May
-
J. E. Smith and A. R. Pleszkun. Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37:562-573, May 1988.
-
(1988)
IEEE Transactions on Computers
, vol.37
, pp. 562-573
-
-
Smith, J.E.1
Pleszkun, A.R.2
-
34
-
-
77956574682
-
Fault tolerant computer architecture
-
D. J. Sorin. Fault Tolerant Computer Architecture. Morgan & Claypool, 2009.
-
(2009)
Morgan & Claypool
-
-
Sorin, D.J.1
-
35
-
-
47349121297
-
-
Standard Performance Evaluation Corporation
-
Standard Performance Evaluation Corporation. SPEC CPU2006, 2006.
-
(2006)
SPEC CPU2006
-
-
-
36
-
-
79955927240
-
Data-Triggered threads: Eliminating redundant computation
-
H.-W. Tseng and D. Tullsen. Data-Triggered threads: Eliminating redundant computation. In HPCA '11.
-
HPCA '11
-
-
Tseng, H.-W.1
Tullsen, D.2
-
37
-
-
0030129806
-
The mips r10000 superscalar microprocessor
-
K. C. Yeager. The MIPS R10000 superscalar microprocessor. IEEE Micro, 16(2):28-40, 1996.
-
(1996)
IEEE Micro
, vol.16
, Issue.2
, pp. 28-40
-
-
Yeager, K.C.1
-
38
-
-
84864863034
-
Two-level adaptive training branch prediction
-
T.-Y. Yeh and Y. N. Patt. Two-level adaptive training branch prediction. In MICRO '91.
-
MICRO '91
-
-
Yeh, T.-Y.1
Patt, Y.N.2
|