Encore: Low-cost, fine-grained transient fault recovery

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 398-409

  Feng, Shuguang ^a   Gupta, Shantanu ^a   Ansari, Amin ^a   Mahlke, Scott A ^a   August, David I ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BATTERY LIFE; CHECK POINTING; CODE TRANSFORMATION; COMMODITY PROCESSORS; CONSUMER DEMANDS; DESIGN CONSTRAINTS; DETECTION SCHEME; FAULTRECOVERY MECHANISMS; FIRST-ORDER; HARDWARE SUPPORTS; NON-INTRUSIVE TECHNIQUES; OUT OF ORDER; PROCESSOR RELIABILITY; PROFILE DATA; PROGRAM ANALYSIS; RECOVERY MECHANISMS; ROLLBACK AND RECOVERY; ROLLBACK RECOVERY; RUNTIME OVERHEADS; SILICON TECHNOLOGIES; SOFTWARE-BASED; SPECIALIZED HARDWARE; TRANSIENT FAULTS; TRANSIENT-FAULT DETECTION;

COSINE TRANSFORMS; COSTS; FAULT DETECTION; FAULT TREE ANALYSIS; RECOVERY;

COST BENEFIT ANALYSIS;

EID: 84863372488     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155667     Document Type: Conference Paper

References (30)

1. D. Bernick, B. Bruckert, P. D. Vigna, D. Garcia, R. Jardine, J. Klecka, and J. Smullen. Nonstop advanced architecture. In International Conference on Dependable Systems and Networks, pages 12-21, June 2005.
2. J. A. Blome, S. Gupta, S. Feng, S. Mahlke, and D. Bradley. Cost-efficient soft error protection for embedded microprocessors. In Proc. of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, pages 421-431, 2006.
3. M. de Kruijf, S. Nomura, and K. Sankaralingam. Relax: An architectural framework for software recovery of hardware faults. In Proc. of the 37th Annual International Symposium on Computer Architecture, pages 497-508, June 2010.
4. X. Dong, Y. Xie, N. Muralimanohar, and N. P. Jouppi. A case study of incremental and background hybrid in-memory checkpointing. In Proc. of the 2010 Exascale Evaluation and Research Techniques Workshop, 2010.
5. R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. Near-threshold computing: Reclaiming moore's law through energy efficient integrated circuits. Proceedings of the IEEE, 98(2):253-266, Feb. 2010.
6. J. Duell, P. Hargrove, and E. Roman. The design and implementaion of berkeley lab's linux checkpoint/restart, 2002.
7. R. Ernst and W. Ye. Embedded program timing analysis based on path clustering and architecture classification. In Proc. of the 1997 International Conference on Computer Aided Design, pages 598-604, 1997.
8. S. Feng, S. Gupta, A. Ansari, and S. Mahlke. Shoestring: Probabilistic soft-error reliability on the cheap. In 18th International Conference on Architectural Support for Programming Languages and Operating Systems, Mar. 2010.
9. S. W. Kim, C.-L. Ooi, R. Eigenmann, B. Falsafi, and T. Vijaykumar. Reference idempotency analysis: A framework for optimizing speculative execution. In Proc. of the 6th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pages 2-11, 2001.
10. M.-L. Li, P. Ramachandran, S. K. Sahoo, S. V. Adve, V. S. Adve, and Y. Zhou. Understanding the propagation of hard errors to software and implications for resilient system design. In 16th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 265-276, 2008.
11. X. Li and D. Yeung. Application-level correctness and its impact on fault tolerance. In Proc. of the 13th International Symposium on High-Performance Computer Architecture, pages 181-192, Feb. 2007.
12. A. Meixner, M. Bauer, and D. Sorin. Argus: Low-cost, comprehensive error detection in simple cores. IEEE Micro, 28(1):52-59, 2008. (Pubitemid 351447391)
13. H. G. Naik, R. Gupta, and P. Beckman. Analyzing checkpointing trends for applications on the ibm blue gene/p system. Proc. of the 2009 International Conference on Parallel ProcessingWorkshops, pages 81-88, 2009.
14. N. Nakka, K. Pattabiraman, and R. Iyer. Processor-level selective replication. In Proc. of the 2007 International Conference on Dependable Systems and Networks, 2007.
15. K. Pattabiraman, Z. Kalbarczyk, and R. K. Iyer. Automated derivation of application-aware error detectors using static analysis: The trusted illiac approach. IEEE Transactions on Dependable and Secure Computing, 99(PrePrints), 2009.
16. M. Prvulovic, Z. Zhang, and J. Torrellas. Revive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors. Proc. of the 29th Annual International Symposium on Computer Architecture, pages 111-122, 2002.
17. P. Racunas, K. Constantinides, S. Manne, and S. Mukherjee. Perturbation-based fault screening. In Proc. of the 13th International Symposium on High-Performance Computer Architecture, pages 169-180, Feb. 2007.
18. V. Reddy, S. Parthasarathy, and E. Rotenberg. Understanding prediction-based partial redundant threading for low-overhead, high-coverage fault tolerance. In 14th International Conference on Architectural Support for Programming Languages and Operating Systems, pages 83-94, Oct. 2006.
19. S. K. Reinhardt and S. S. Mukherjee. Transient fault detection via simulataneous multithreading. In Proc. of the 27th Annual International Symposium on Computer Architecture, pages 25-36, June 2000.
20. G. Reis, J. Chang, N. Vachharajani, R. Rangan, and D. I. August. SWIFT: Software implemented fault tolerance. In Proc. of the 2005 International Symposium on Code Generation and Optimization, pages 243-254, 2005.
21. E. Rotenberg. AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. In International Symposium on Fault Tolerant Computing, pages 84-91, 1999.
22. S. K. Sahoo, M.-L. Li, P. Ramchandran, S. Adve, V. Adve, and Y. Zhou. Using likely program invariants for hardware reliability. In Proc. of the 2008 International Conference on Dependable Systems and Networks, 2008.
23. N. Shanbhag, R. Abdallah, R. Kumar, and D. Jones. Stochastic computation. In Proc. of the 47th Design Automation Conference, 2010.
24. J. Sloan, D. Kesler, R. Kumar, and A. Rahimi. A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance. In Proc. of the 2010 International Conference on Dependable Systems and Networks, 2010.
25. J. C. Smolens, B. T. Gold, B. Falsafi, and J. C. Hoe. Reunion: Complexity-effective multicore redundancy. In Proc. of the 39th Annual International Symposium on Microarchitecture, pages 223-234, 2006.
26. D. Sorin, M. Martin, M. Hill, and D. Wood. Safetynet: improving the availability of shared memory multiprocessors with global checkpoint/recovery. Proc. of the 29th Annual International Symposium on Computer Architecture, pages 123-134, 2002.
27. L. Spainhower and T. Gregg. IBM S/390 Parallel Enterprise Server G5 Fault Tolerance: A Historical Perspective. IBM Journal of Research and Development, 43(6):863-873, 1999.
28. V. Sridharan and D. R. Kaeli. Eliminating microarchitectural dependency from architectural vulnerability. In Proc. of the 15th International Symposium on High-Performance Computer Architecture, pages 117-128, 2009.
29. N. J. Wang and S. J. Patel. ReStore: Symptom-based soft error detection in microprocessors. IEEE Transactions on Dependable and Secure Computing, 3(3):188-201, June 2006.
30. N. J. Warter and W.-M. W. Hwu. A software based approach to achieving optimal performance for signature control flow checking. In Proc. of the 1998 International Symposium on Fault-Tolerant Computing, pages 442-449, 1990.