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Volumn , Issue , 2011, Pages 140-151

Idempotent processor architecture

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK SUITES; BRANCH PREDICTION; DEPENDENCE PREDICTION; EXECUTION PARADIGM; GEOMETRIC MEAN; HARDWARE COMPLEXITY; HARDWARE FAULTS; OUT OF ORDER; PROCESSOR ARCHITECTURES; QUANTITATIVE RESULT; RE-EXECUTION; SPECULATIVE EXECUTION; TECHNOLOGY SCALING;

EID: 84858772630     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155637     Document Type: Conference Paper
Times cited : (38)

References (41)
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    • Veal: Virtualized execution accelerator for loops
    • N. Clark, A. Hormati, and S. Mahlke. Veal: Virtualized execution accelerator for loops. In ISCA '08, pages 389-400.
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    • Superscalar instruction execution in the 21164 alpha microprocessor
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    • Dynamically specialized datapaths for energy efficient computing
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.