Recovery-based design for variation-tolerant SoCs

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 826-833

  Kozhikkottu, Vivek ^a   Dey, Sujit ^b   Raghunathan, Anand ^a  

^a Purdue University   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

low power design; system on chip; variation aware design; variation tolerance

Indexed keywords

CMOS SCALING; CONVENTIONAL DESIGN; DESIGN PARADIGM; LEVELS OF ABSTRACTION; LOW-POWER DESIGN; MAC PROCESSORS; MICRO ARCHITECTURES; NANO-METER REGIMES; OPTIMAL OPERATING POINT; PARAMETER VARIATION; PERFORMANCE PENALTIES; RECOVERY ISLANDS; SOC DESIGNS; SYSTEM LEVELS; SYSTEM ON CHIPS; VARIATION TOLERANCES; VARIATION-AWARE DESIGN; WIRELESS VIDEO;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMERCE; COMPUTER AIDED DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; MOTION PICTURE EXPERTS GROUP STANDARDS;

RECOVERY;

EID: 84863549098     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228510     Document Type: Conference Paper

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