Optimal power/Performance pipelining for error resilient processors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2010, Pages 356-363

  Zea, Nicolas ^a   Sartori, John ^a   Ahrens, Ben ^a   Kumar, Rakesh ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; ANALYTICAL RESULTS; CIRCUIT STRUCTURES; CYCLE-ACCURATE SIMULATION; DESIGN METHODOLOGY; EFFICIENCY BENEFITS; ENERGY SAVING; ERROR RATE; ERROR RECOVERY MECHANISMS; ERROR RESILIENCE; ERROR RESILIENCY; ERROR-RESILIENT; INPUT VOLTAGES; MICRO ARCHITECTURES; NOMINAL OPERATING POINT; PIPELINE DEPTH; PIPELINE STRUCTURE; PROCESSOR DESIGN; PROCESSOR PIPELINES; RECOVERY OVERHEAD;

COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; ENERGY EFFICIENCY; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; OPTIMIZATION; PIPELINES; STRUCTURAL DESIGN; WALLS (STRUCTURAL PARTITIONS);

PIPELINE PROCESSING SYSTEMS;

EID: 78650739105     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2010.5647702     Document Type: Conference Paper

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