System-level mitigation of WID leakage power variability using body-bias islands

Embedded Systems Week 2008 - Proceedings of the 6th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008

Volumn , Issue , 2008, Pages 273-278

  Garg, Siddharth ^a   Marculescu, Diana ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE BODY BIASING; BASELINE SYSTEMS; BODY BIAS; DESIGN TIME; GLOBAL CLOCKS; LEAKAGE POWER; MANUFACTURING PROCESS VARIATIONS; MONTE-CARLO; MULTI PROCESSOR SYSTEMS; PARTITIONING TECHNIQUES; PERFORMANCE METRICS; POST FABRICATIONS; PROCESSING ELEMENTS; RUN-TIME; STANDARD DEVIATIONS; SYSTEM LEVELS;

BIAS VOLTAGE; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUITS; LEAKAGE CURRENTS;

EMBEDDED SYSTEMS;

EID: 63349103590     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450135.1450197     Document Type: Conference Paper

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