Single event upsets in deep-submicrometer technologies due to charge sharing

IEEE Transactions on Device and Materials Reliability

Volumn 8, Issue 3, 2008, Pages 582-589

  Amusan, Oluwole A ^a   Massengill, Lloyd W ^a   Baze, Mark P ^b   Sternberg, Andrew L ^a   Witulski, Arthur F ^a   Bhuva, Bharat L ^a   Black, Jeffrey D ^a  

^a VANDERBILT UNIVERSITY   (United States)

^b BOEING COMPANY   (United States)

Author keywords

Alpha particles; Charge sharing; Dual interlocked cell (DICE) latch; Neutrons; Parasitic bipolar transistor; Radiation hardened by design; Single event circuit characterization; Single event upset (SEU)

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER AIDED DESIGN; ELECTRIC NETWORK ANALYSIS; ENERGY TRANSFER; HARDENING; LIGHTING FIXTURES; RADIATION HARDENING; RADIATION PROTECTION; STATIC RANDOM ACCESS STORAGE;

CHARGE SHARING; DUAL INTERLOCKED CELL (DICE) LATCH; PARASITIC BIPOLAR TRANSISTOR; RADIATION HARDENED BY DESIGN; SINGLE EVENT CIRCUIT CHARACTERIZATION; SINGLE EVENT UPSET (SEU);

TECHNOLOGY TRANSFER;

EID: 54949096192     PISSN: 15304388     EISSN: 15304388     Source Type: Journal    
DOI: 10.1109/TDMR.2008.2000892     Document Type: Article

References (20)

1. W. Peterson, Error-Correcting Codes, 2nd ed. Cambridge, MA: MIT Press, 1980. 560 p.
2. S. E. Diehl, A. Ochoa, P. V. Dressendorfer, R. Koga, and W. A. Koloasinski, "Error analysis and prevention of cosmic ion-induced soft errors in static CMOS RAMS," IEEE Trans. Nucl. Sci., vol. NS-29, no. 6, pp. 2032-2039, Dec. 1982.
3. A. Balasubramanian, B. L. Bhuva, J. D. Black, and L. W. Massengill, "RHBD techniques for mitigating effects of single event hits using guardgates," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2531-2535, Dec. 2005.
4. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996.
5. R. Velazco, T. Calin, M. Nicolaidis, S. C. Moss, S. D. LaLumondiere, V. T. Tran, and R. Koga, "SEU-hardened storage cell validation using a pulsed laser," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2843-2848, Dec. 1996.
6. B. D. Olson, D. R. Ball, K. M. Warren, L. W. Massengill, N. F. Haddad, S. E. Doyle, and D. McMorrow, "Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2132-2136, Dec. 2005.
7. J. D. Black, A. L. Sternberg, M. L. Alles, A. F. Witulski, B. L. Bhuva, L. W. Massengill, J. M. Benedetto, M. P. Baze, J. L. Wert, and M. G. Hubert, "HBD layout isolation techniques for multiple node charge collection mitigation," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2536-2541, Dec. 2005.
8. O. A. Amusan, A. F. Witulski, L. W. Massengill, B. L. Bhuva, P. R. Fleming, M. L. Alles, A. L. Sternberg, J. D. Black, and R. D. Schrimpf, "Charge collection and charge sharing in a 130 nm CMOS technology," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3253-3258, Dec. 2006.
9. R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Trans. Device Mater. Rel., vol. 5, no. 3, pp. 305-316, Sep. 2005.
10. N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, B. Gill, and J. Maiz, "Radiation-induced soft error rates of advanced CMOS bulk devices," in Proc. IEEE Conf. 44th Annu. Int. Rel. Phys. Symp., 2006, pp. 217-225.
11. L. W. Massengill, "SEU modeling and prediction techniques," in Proc. IEEE NSREC Short Course, 1993, pp. III-1-III-93.
12. P. E. Dodd and L. W. Massengill, "Basic mechanisms and modeling of single-event upset in digital microelectronics," IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583-602, Jun. 2003.
13. M. P. Baze, J. Wert, A. F. Witulski, D. McMorrow, J. W. Clement, and M. G. Hubert, "Heavy ion test results on 13 shift registers in a 130 nm process," presented at the Single Event Effects Symp., Long Beach, CA.
14. Synopsys User Manual Release 10, Synopsys, Mountain View, CA.
15. [Online]. Available: http://www.itrs.net/Common/2004Update/ 2004Update.htm
16. Nvidia GeForceFX 5700 Ultra Graphics Processor Structural Analysis (SAR-0408-002), CHIPWORKS Inc., Ottawa, ON, Canada, 2005.
17. O. A. Amusan, L. W. Massengill, M. P. Baze, B. L. Bhuva, A. F. Witulski, S. DasGupta, A. L. Sternberg, P. R. Fleming, C. C. Heath, and M. L. Alles, "Directional sensitivity of single event upsets in 90 nm CMOS due to charge sharing," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2584-2589, Dec. 2007.
18. X. Zhu, X. Deng, R. Baumann, and S. Krishnan, "A quantitative assessment of charge collection efficiency of N+ and P+ diffusion areas in terrestrial neutron environment," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2156-2161, Dec. 2007.
19. L. W. Massengill, O. A. Amusan, S. Dasgupta, A. L. Sternberg, J. D. Black, A. F. Wituski, B. L. Bhuva, and M. L. Alles, "Soft-error charge-sharing mechanisms at sub-100 nm technology nodes," in Proc. IEEE Int. Conf. Integr. Circuit Des. Technol., 2007, pp. 213-217.
20. J. Benedetto, C. Salomonson-Begay, and P. McGuirk, "Single event upset hardening limitations in deep sub-micron digital designs due to critical node crowding," presented at the HEART, Tampa, FL, 2005.