Effects of multi-node charge collection in flip-flop designs at advanced technology nodes

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 1026-1030

  Sheshadri, Vijay B ^a   Bhuva, Bharat L ^a   Reed, Robert A ^a   Weller, Robert A ^a   Mendenhall, Marcus H ^a   Schrimpf, Ron D ^a   Warren, Kevin M ^a   Sierawski, Brian D ^a   Wen, Shi Jie ^b   Wong, Rick ^b  

^a VANDERBILT UNIVERSITY   (United States)

^b CISCO SYSTEMS   (United States)

Author keywords

Charge sharing; Component; DFF; DICE; Flip flops; MRED; Multi node upsets

Indexed keywords

CHARGE SHARING; COMPONENT; DFF; DICE; FLIP-FLOPS; MRED; MULTI-NODE UPSETS;

DESIGN; THREE DIMENSIONAL;

FLIP FLOP CIRCUITS;

EID: 77957891797     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488683     Document Type: Conference Paper

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