SEU critical charge and sensitive area in A submicron CMOS technology

IEEE Transactions on Nuclear Science

Volumn 44, Issue 6 PART 1, 1997, Pages 2266-2273

  Detcheverry, C ^a,b   Dachs, C ^a   Lorfevre E ^a,b   Sudre, C ^a   Bruguier, G ^a,b   Palau, J M ^a,b   Gasiot, J ^b   Ecoffet, R ^a,b  

^a UNIV MONTPELLIER   (France)

^b CNES   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CHARGE; INTEGRATED CIRCUIT TESTING; RADIATION EFFECTS;

MIXED MODE SIMULATION; SINGLE EVENT UPSET (SEU); STATIC RANDOM ACCESS MEMORY (SRAM); SUBMICRON TECHNOLOGY;

RANDOM ACCESS STORAGE;

EID: 0031338054     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.659045     Document Type: Article

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