Accurate leakage estimation for FinFET standard cells using the response surface methodology

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2012, Pages 238-244

  Chaudhuri, Sourindra ^a   Mishra, Prateek ^a   Jha, Niraj K ^a  

^a Princeton University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CENTRAL COMPOSITE ROTATABLE DESIGN; CIRCUIT DESIGNERS; CIRCUIT DESIGNS; COST-EFFECTIVE FABRICATION; CPU TIME; DEVICE PERFORMANCE; ENVIRONMENTAL VARIATIONS; ERROR RANGE; FIN THICKNESS; FINFET DEVICES; FINFETS; GATE LENGTH; GATE OXIDE; LEAKAGE ESTIMATION; LEAKAGE MODEL; LEAKAGE POWER CONSUMPTION; LOGIC STYLE; MODELING TECHNIQUE; ORDERS OF MAGNITUDE; QUASI-MONTE CARLO; RESPONSE SURFACE METHODOLOGY; ROOT MEAN SQUARE ERRORS; STANDARD CELL; TCAD SIMULATION; TECHNOLOGY NODES; TIMING CHARACTERIZATION; TRIGATE;

ANALYTICAL MODELS; ELECTRIC BATTERIES; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MEAN SQUARE ERROR; MODELS; MONTE CARLO METHODS; MOSFET DEVICES; NANOTECHNOLOGY; SURFACE PROPERTIES; THREE DIMENSIONAL COMPUTER GRAPHICS;

THREE DIMENSIONAL;

EID: 84859906521     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2012.77     Document Type: Conference Paper

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