Integration and frequency dependent parametric modeling of Through Silicon Via involved in high density 3D chip stacking

ECS Transactions

Volumn 33, Issue 12, 2010, Pages 1-21

  Cadix, L ^a,b   Fuchs, C ^c   Rousseau, M ^a   Leduc, P ^c   Chaabouni, H ^b   Thuaire, A ^c   Brocard, M ^a   Valentian, A ^c   Farcy, A ^a   Bermond, C ^b   Sillon, N ^c   Ancey, P ^a   Flechet B ^b  

^a STMICROELECTRONICS   (France)

^b UNIVERSITÉ DE SAVOIE   (France)

^c CEA LETI   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; CMOS INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; INTEGRATION; SILICON WAFERS; WAFER BONDING;

ELECTRICAL PERFORMANCE; FREQUENCY DEPENDENT; PARAMETRIC MODELING; RF CHARACTERIZATION; SIGNAL PROPAGATION; SUBSTRATE EFFECTS; THROUGH-SILICON-VIA; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84857376831     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3501030     Document Type: Conference Paper

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