A 3D packaging technology for high-density stacked DRAM

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2007, Pages

  Kawano, Masaya ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

MICROPROCESSOR CHIPS; OPTIMIZATION; PACKAGING; POLYSILICON; THREE DIMENSIONAL; WAFER BONDING;

FEEDTHROUGH INTERPOSER (FTI); LOW-COST BONDING; SMAFTI TECHNOLOGY; THROUGH-SILICON VIAS (TSV);

DYNAMIC RANDOM ACCESS STORAGE;

MICROPROCESSORS; PACKAGING; POLYSILICONES;

EID: 34548863641     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2007.378921     Document Type: Conference Paper

References (6)

1. A. Klumpp, R Merkel, R. Wieland, and P. Ramm, "Chip-to-Wafer Stacking Technology for 3D System Integration", 2003 Proceedings of 53rd Electronic Components & Technology Conference (ECTC 2003), pp. 1080-1083.
2. K. Takahashi et al., "Process Integration of 3D Chip Stack with Vertical Interconnection", 2004 Proceedings of 54th Electronic Components & Technology Conference (ECTC 2004), pp. 601-609.
3. T. Fukushima, Y. Yamada, H. Kikuchi, and M. Koyanagi, "New Three-Dimensional Integration Technology Using Self-Assembly Technique", International Electron Devices Meeting Technical Digest (IEDM 2005), pp. 348-351.
4. H. Ikeda, M. Kawano, and T. Mitsuhashi, "Stacked Memory Chip Technology Development", SEMI Technology Symposium (STS) 2005 Proceedings, Session 9 pp. 37-42.
5. Y. Kurita, et al., "A Novel SMAFTI Package for Inter-Chip Wide-Band Data Transfer", 2006 Proceedings of 56th Electronic Components & Technology Conference (ECTC 2006), pp. 289-297.
6. M. Kawano, et al., "A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer", International Election Devices Meeting Technical Digest (IEDM 2006), pp. 581-584.